From 181e2d445ce0e9b2fa0a04c4d4c4a4b6b75f5ea0 Mon Sep 17 00:00:00 2001
From: Furquan Shaikh <furquan@google.com>
Date: Mon, 1 Jun 2020 13:03:45 -0700
Subject: northbridge/intel/haswell: Update hostbridge.asl to ASL2.0

This change updates hostbridge.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.

TEST=Verified using --timeless option to abuild that the resulting
coreboot.rom is same as without the ASL2.0 syntax changes for
google/beltino.

Change-Id: I0ba2da441c7b398cc7f84a7ef7a5d233b0365cbe
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/northbridge/intel/haswell/acpi/hostbridge.asl | 81 +++++++++++------------
 1 file changed, 40 insertions(+), 41 deletions(-)

(limited to 'src/northbridge/intel/haswell')

diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl
index d8e35d337e..8fbfabfa71 100644
--- a/src/northbridge/intel/haswell/acpi/hostbridge.asl
+++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl
@@ -141,17 +141,16 @@ Device (MCHC)
 	External (\_SB.CP00._PSS)
 	Method (PSSS, 1, NotSerialized)
 	{
-		Store (One, Local0) /* Start at P1 */
-		Store (SizeOf (\_SB.CP00._PSS), Local1)
+		Local0 = One /* Start at P1 */
+		Local1 = SizeOf (\_SB.CP00._PSS)
 
-		While (LLess (Local0, Local1)) {
+		While (Local0 < Local1) {
 			/* Store _PSS entry Control value to Local2 */
-			ShiftRight (DeRefOf (Index (DeRefOf (Index
-			      (\_SB.CP00._PSS, Local0)), 4)), 8, Local2)
-			If (LEqual (Local2, Arg0)) {
-				Return (Subtract (Local0, 1))
+			Local2 = DeRefOf (Index (DeRefOf (Index (\_SB.CP00._PSS, Local0)), 4)) >> 8
+			If (Local2 == Arg0) {
+				Return (Local0 - 1)
 			}
-			Increment (Local0)
+			Local0++
 		}
 
 		Return (0)
@@ -162,10 +161,10 @@ Device (MCHC)
 	{
 		If (\ISLP ()) {
 			/* Haswell ULT PL2 = 25W */
-			Return (Multiply (25, 8))
+			Return (25 * 8)
 		} Else {
 			/* Haswell Mobile PL2 = 1.25 * PL1 */
-			Return (Divide (Multiply (Arg0, 125), 100))
+			Return ((Arg0 * 125) / 100)
 		}
 	}
 
@@ -183,23 +182,23 @@ Device (MCHC)
 		Store ("Set TDP Down", Debug)
 
 		/* Set CTC */
-		Store (CTCD, CTCS)
+		CTCS = CTCD
 
 		/* Set TAR */
-		Store (TARD, TARS)
+		TARS = TARD
 
 		/* Set PPC limit and notify OS */
-		Store (PSSS (TARD), PPCM)
+		PPCM = PSSS (TARD)
 		PPCN ()
 
 		/* Set PL2 */
-		Store (CPL2 (CTDD), PL2V)
+		PL2V = CPL2 (CTDD)
 
 		/* Set PL1 */
-		Store (CTDD, PL1V)
+		PL1V = CTDD
 
 		/* Store the new TDP Down setting */
-		Store (CTCD, CTCC)
+		CTCC = CTCD
 
 		Release (CTCM)
 		Return (1)
@@ -211,7 +210,7 @@ Device (MCHC)
 		If (Acquire (CTCM, 100)) {
 			Return (0)
 		}
-		If (LEqual (CTCN, CTCC)) {
+		If (CTCN == CTCC) {
 			Release (CTCM)
 			Return (0)
 		}
@@ -219,23 +218,23 @@ Device (MCHC)
 		Store ("Set TDP Nominal", Debug)
 
 		/* Set PL1 */
-		Store (CTDN, PL1V)
+		PL1V = CTDN
 
 		/* Set PL2 */
-		Store (CPL2 (CTDN), PL2V)
+		PL2V = CPL2 (CTDN)
 
 		/* Set PPC limit and notify OS */
-		Store (PSSS (TARN), PPCM)
+		PPCM = PSSS (TARN)
 		PPCN ()
 
 		/* Set TAR */
-		Store (TARN, TARS)
+		TARS = TARN
 
 		/* Set CTC */
-		Store (CTCN, CTCS)
+		CTCS = CTCN
 
 		/* Store the new TDP Nominal setting */
-		Store (CTCN, CTCC)
+		CTCC = CTCN
 
 		Release (CTCM)
 		Return (1)
@@ -244,7 +243,7 @@ Device (MCHC)
 	/* Calculate PL1 value based on requested TDP */
 	Method (TDPP, 1, NotSerialized)
 	{
-		Return (Multiply (ShiftLeft (Subtract (PUNI, 1), 2), Arg0))
+		Return (((PUNI - 1) << 2) * Arg0)
 	}
 
 	/* Enable Controllable TDP to limit PL1 to requested value */
@@ -257,19 +256,19 @@ Device (MCHC)
 		Store ("Enable PL1 Limit", Debug)
 
 		/* Set _PPC to LFM */
-		Store (PSSS (LFM_), Local0)
-		Add (Local0, 1, PPCM)
+		Local0 = PSSS (LFM_)
+		PPCM = Local0 + 1
 		\PPCN ()
 
 		/* Set TAR to LFM-1 */
-		Subtract (LFM_, 1, TARS)
+		TARS = LFM_ - 1
 
 		/* Set PL1 to desired value */
-		Store (PL1V, SPL1)
-		Store (TDPP (Arg0), PL1V)
+		SPL1 = PL1V
+		PL1V = TDPP (Arg0)
 
 		/* Set PL1 CLAMP bit */
-		Store (One, PL1C)
+		PL1C = 1
 
 		Release (CTCM)
 		Return (1)
@@ -285,16 +284,16 @@ Device (MCHC)
 		Store ("Disable PL1 Limit", Debug)
 
 		/* Clear PL1 CLAMP bit */
-		Store (Zero, PL1C)
+		PL1C = 0
 
 		/* Set PL1 to normal value */
-		Store (SPL1, PL1V)
+		PL1V = SPL1
 
 		/* Set TAR to 0 */
-		Store (Zero, TARS)
+		TARS = 0
 
 		/* Set _PPC to 0 */
-		Store (Zero, PPCM)
+		PPCM = 0
 		\PPCN ()
 
 		Release (CTCM)
@@ -426,18 +425,18 @@ Method (_CRS, 0, Serialized)
 
 	// Fix up PCI memory region
 	// Start with Top of Lower Usable DRAM
-	Store (^MCHC.TLUD, Local0)
-	Store (^MCHC.MEBA, Local1)
+	Local0 = ^MCHC.TLUD
+	Local1 = ^MCHC.MEBA
 
 	// Check if ME base is equal
-	If (LEqual (Local0, Local1)) {
+	If (Local0 == Local1) {
 		// Use Top Of Memory instead
-		Store (^MCHC.TOM, Local0)
+		Local0 = ^MCHC.TOM
 	}
 
-	Store (Local0, PMIN)
-	Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX)
-	Add(Subtract(PMAX, PMIN), 1, PLEN)
+	PMIN = Local0
+	PMAX = CONFIG_MMCONF_BASE_ADDRESS - 1
+	PLEN = PMAX - PMIN + 1
 
 	Return (MCRS)
 }
-- 
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