From 05f996d433ef91e699503e1ef679f6cafdf00d3b Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 6 Jul 2020 22:10:37 +0200 Subject: nb/intel/haswell/acpi: Fix host bridge registers The host bridge register definitions haven't changed from Sandy Bridge to Haswell, according to the datasheets. However, coreboot's ACPI code is not the same. Looks like Haswell values are wrong, so correct them. Change-Id: Ib099575b5cc5e7d468db51f382a15b8aac3eedea Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/43151 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Nico Huber --- src/northbridge/intel/haswell/acpi/hostbridge.asl | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) (limited to 'src/northbridge/intel/haswell') diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index dd4b79a6cf..0f2ed1625b 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - Name(_HID,EISAID("PNP0A08")) // PCIe Name(_CID,EISAID("PNP0A03")) // PCI @@ -16,24 +15,24 @@ Device (MCHC) Offset (0x40), // EPBAR EPEN, 1, // Enable , 11, // - EPBR, 24, // EPBAR + EPBR, 27, // EPBAR Offset (0x48), // MCHBAR MHEN, 1, // Enable - , 13, // - MHBR, 22, // MCHBAR + , 14, // + MHBR, 24, // MCHBAR Offset (0x54), DVEN, 32, Offset (0x60), // PCIe BAR PXEN, 1, // Enable PXSZ, 2, // BAR size , 23, // - PXBR, 10, // PCIe BAR + PXBR, 13, // PCIe BAR Offset (0x68), // DMIBAR DMEN, 1, // Enable , 11, // - DMBR, 24, // DMIBAR + DMBR, 27, // DMIBAR Offset (0x70), // ME Base Address MEBA, 64, -- cgit v1.2.3