From 03f0e43a3c4172941f2eadf30f89413632b90cb4 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Jul 2020 13:51:15 +0200 Subject: haswell: Drop GPIO indirection layers This simplifies things and makes type checking possible. Change-Id: Iefc9baabae286aac2f2c46853adf1f6edf01586f Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/43103 Tested-by: build bot (Jenkins) Reviewed-by: Tristan Corrick --- src/northbridge/intel/haswell/romstage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/northbridge/intel/haswell/romstage.c') diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index c3d9a1088a..8cf2e7ca71 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -19,7 +19,7 @@ void romstage_common(const struct romstage_params *params) enable_lapic(); - wake_from_s3 = early_pch_init(params->gpio_map); + wake_from_s3 = early_pch_init(); /* Perform some early chipset initialization required * before RAM initialization can work -- cgit v1.2.3