From 45f448f4a4e09b270d964c98d3aced2e73d9d6bc Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Jul 2020 14:46:47 +0200 Subject: haswell: Relocate `mainboard_romstage_entry` to northbridge This is what sandybridge does, and if done properly allows factoring out common settings. Said refactoring will be handled in subsequent commits. Change-Id: I075eba1324a9e7cbd47e776b097eb940102ef4fe Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/43108 Tested-by: build bot (Jenkins) Reviewed-by: Tristan Corrick --- src/northbridge/intel/haswell/raminit.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/northbridge/intel/haswell/raminit.h') diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h index 920ee0fabd..140ea2088d 100644 --- a/src/northbridge/intel/haswell/raminit.h +++ b/src/northbridge/intel/haswell/raminit.h @@ -8,6 +8,9 @@ /* Optional function to copy SPD data for on-board memory */ void copy_spd(struct pei_data *peid); +/* Necessary function to initialize pei_data with mainboard-specific settings */ +void mainboard_fill_pei_data(struct pei_data *pei_data); + void sdram_initialize(struct pei_data *pei_data); void setup_sdram_meminfo(struct pei_data *pei_data); int fixup_haswell_errata(void); -- cgit v1.2.3