From 190688c65f7c128f2dace3b600d1c0f2e56723ee Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Tue, 13 Aug 2013 11:18:42 -0700 Subject: haswell: add option to change DqPinsInterleaved Some mainboards will need to have this set. Signed-off-by: Stefan Reinauer Change-Id: I4732a9af822a60b5050d03d2ac4bb7cbd6c723d0 Reviewed-on: https://gerrit.chromium.org/gerrit/65722 Reviewed-by: Aaron Durbin Tested-by: Stefan Reinauer Commit-Queue: Stefan Reinauer Reviewed-on: http://review.coreboot.org/4474 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/northbridge/intel/haswell/pei_data.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/northbridge/intel/haswell/pei_data.h') diff --git a/src/northbridge/intel/haswell/pei_data.h b/src/northbridge/intel/haswell/pei_data.h index f9d6e8b16a..f92c0a68e0 100644 --- a/src/northbridge/intel/haswell/pei_data.h +++ b/src/northbridge/intel/haswell/pei_data.h @@ -31,7 +31,7 @@ #define PEI_DATA_H typedef void (*tx_byte_func)(unsigned char byte); -#define PEI_VERSION 14 +#define PEI_VERSION 15 #define MAX_USB2_PORTS 16 #define MAX_USB3_PORTS 16 @@ -92,6 +92,7 @@ struct pei_data int dimm_channel1_disabled; /* Enable 2x Refresh Mode */ int ddr_refresh_2x; + int dq_pins_interleaved; /* Data read from flash and passed into MRC */ unsigned char *mrc_input; unsigned int mrc_input_len; -- cgit v1.2.3