From fa0725dead0fdc7e9330e77c42ff4ed4b36a89c4 Mon Sep 17 00:00:00 2001 From: Ryan Salsamendi Date: Fri, 30 Jun 2017 17:29:37 -0700 Subject: northbridge/intel/haswell: Fix undefined behavior Fix reports found by undefined behavior sanitizer. Left shifting an int where the right operand is >= the width of the type is undefined. Add UL suffix since it's safe for unsigned types. Change-Id: If2d34e4f05494c17bf9b9dec113b8f6863214e56 Signed-off-by: Ryan Salsamendi Reviewed-on: https://review.coreboot.org/20447 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Paul Menzel --- src/northbridge/intel/haswell/northbridge.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) (limited to 'src/northbridge/intel/haswell/northbridge.c') diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index a8c8015d97..32be916a45 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -36,6 +36,7 @@ static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) { u32 pciexbar_reg; + u32 mask; *base = 0; *len = 0; @@ -47,15 +48,20 @@ static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) switch ((pciexbar_reg >> 1) & 3) { case 0: // 256MB - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); + mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); + *base = pciexbar_reg & mask; *len = 256 * 1024 * 1024; return 1; case 1: // 128M - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); + mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); + mask |= (1 << 27); + *base = pciexbar_reg & mask; *len = 128 * 1024 * 1024; return 1; case 2: // 64M - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); + mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); + mask |= (1 << 27) | (1 << 26); + *base = pciexbar_reg & mask; *len = 64 * 1024 * 1024; return 1; } -- cgit v1.2.3