From 1fc0edd9fe6b8072a87dce769789119e81af978b Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 31 May 2020 00:03:28 +0200 Subject: src: Use pci_dev_ops_pci where applicable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ie004a94a49fc8f53c370412bee1c3e7eacbf8beb Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/41944 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner Reviewed-by: Paul Menzel Reviewed-by: Nico Huber --- src/northbridge/intel/haswell/northbridge.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'src/northbridge/intel/haswell/northbridge.c') diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index c282aea044..ef7742e523 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -447,17 +447,13 @@ static void northbridge_init(struct device *dev) MCHBAR32(MMIO_PAVP_MSG) = 0x00100001; } -static struct pci_operations intel_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations mc_ops = { .read_resources = mc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, .acpi_fill_ssdt = generate_cpu_entries, - .ops_pci = &intel_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short mc_pci_device_ids[] = { -- cgit v1.2.3