From f95b9b4b092837663b6fa1cf42ce312338dee5c3 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 20 Jan 2021 01:10:48 +0100 Subject: nb/intel/haswell: Use common {DMI,EP,MCH}BAR accessors Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I3ff4577ce662697cb3d8fb34003217fd6275dd42 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/49749 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: HAOUAS Elyes --- src/northbridge/intel/haswell/early_init.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'src/northbridge/intel/haswell/early_init.c') diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index a0e4211f02..f81ff9fede 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -14,12 +14,12 @@ static void haswell_setup_bars(void) { printk(BIOS_DEBUG, "Setting up static northbridge registers..."); /* Set up all hardcoded northbridge BARs */ - pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1); - pci_write_config32(HOST_BRIDGE, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); - pci_write_config32(HOST_BRIDGE, MCHBAR, DEFAULT_MCHBAR | 1); - pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); - pci_write_config32(HOST_BRIDGE, DMIBAR, DEFAULT_DMIBAR | 1); - pci_write_config32(HOST_BRIDGE, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32); + pci_write_config32(HOST_BRIDGE, EPBAR, CONFIG_FIXED_EPBAR_MMIO_BASE | 1); + pci_write_config32(HOST_BRIDGE, EPBAR + 4, 0); + pci_write_config32(HOST_BRIDGE, MCHBAR, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR + 4, 0); + pci_write_config32(HOST_BRIDGE, DMIBAR, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1); + pci_write_config32(HOST_BRIDGE, DMIBAR + 4, 0); /* Set C0000-FFFFF to access RAM on both reads and writes */ pci_write_config8(HOST_BRIDGE, PAM0, 0x30); -- cgit v1.2.3