From 6e732d34a0c1b87803925065b66076599c1e5642 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 28 Jan 2021 13:56:18 +0100 Subject: intel: Turn `DEFAULT_RCBA` into a Kconfig symbol Create `FIXED_RCBA_MMIO_BASE` and use it everywhere, except in cases where a pointer cast would be necessary. Instances in Sandy Bridge MRC code were left as-is intentionally, so as not to collide with another cleanup patch train. Tested with BUILD_TIMELESS=1, these boards remain identical: - Asus P8Z77-V LX2 - Packard Bell MS2290 Change-Id: I642958fbd6f02dbf54812d6a75d6bc3087acc77a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/50036 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/acpi/hostbridge.asl | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src/northbridge/intel/haswell/acpi') diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 9a39647c06..50a130694f 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include "../haswell.h" -#include Name (_HID, EISAID ("PNP0A08")) // PCIe Name (_CID, EISAID ("PNP0A03")) // PCI @@ -175,7 +174,7 @@ Device (PDRC) Name (_UID, 1) Name (PDRS, ResourceTemplate () { - Memory32Fixed (ReadWrite, DEFAULT_RCBA, 0x00004000) + Memory32Fixed (ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, 0x00004000) Memory32Fixed (ReadWrite, DEFAULT_MCHBAR, 0x00008000) Memory32Fixed (ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed (ReadWrite, DEFAULT_EPBAR, 0x00001000) -- cgit v1.2.3