From f4fa1e1d06b5c68b746274c39f23cc8b05801d90 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 3 Aug 2020 14:12:13 +0200 Subject: nb/intel/haswell: Deduplicate PCIEXBAR decoding Add `decode_pcie_bar` for consistency with other Intel northbridges. Change-Id: If04ca3467bb067b28605a3acccb8bda325735999 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/44120 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/haswell/acpi.c | 39 ++++-------------------------------- 1 file changed, 4 insertions(+), 35 deletions(-) (limited to 'src/northbridge/intel/haswell/acpi.c') diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index 1df66bc4d1..cc4487c43c 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -10,44 +11,12 @@ unsigned long acpi_fill_mcfg(unsigned long current) { - struct device *dev; - u32 pciexbar = 0; - u32 pciexbar_reg; - int max_buses; - u32 mask; - - dev = pcidev_on_root(0, 0); - if (!dev) - return current; - - pciexbar_reg = pci_read_config32(dev, PCIEXBAR); - - /* MMCFG not supported or not enabled. */ - if (!(pciexbar_reg & (1 << 0))) - return current; + u32 length, pciexbar; - mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); - switch ((pciexbar_reg >> 1) & 3) { - case 0: /* 256MB */ - pciexbar = pciexbar_reg & mask; - max_buses = 256; - break; - case 1: /* 128M */ - mask |= (1 << 27); - pciexbar = pciexbar_reg & mask; - max_buses = 128; - break; - case 2: /* 64M */ - mask |= (1 << 27) | (1 << 26); - pciexbar = pciexbar_reg & mask; - max_buses = 64; - break; - default: /* RSVD */ + if (!decode_pcie_bar(&pciexbar, &length)) return current; - } - if (!pciexbar) - return current; + const int max_buses = length / MiB; current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0, 0, max_buses - 1); -- cgit v1.2.3