From be9533aba957e9c43f77381f436906951c13c98b Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 12 Oct 2019 14:35:25 +0200 Subject: nb/intel/gm45: Add C_ENVIRONMENT_BOOTBLOCK support The i82801ix_early_init is now called both in the bootblock and romstage. The rationale behind setting this up twice is to ensure bootblock-romstage compatibility in the future if for instance VBOOT is used. This moves the console init to the bootblock. The romstage now runs uncached. Adding a prog_run hooks to set up an MTRR to cache the romstage will be done in a followup patch. The default size of 64KiB is not modified for the bootblock as trying to fit both EHCI and SPI flash debugging needs a more space and 64KiB is the next power of 2 size that fits it. TESTED on Thinkpad X200. Change-Id: I8f59736cb54377973215f35e35d2cbcd1d82c374 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/35992 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/northbridge/intel/gm45/Kconfig | 5 +---- src/northbridge/intel/gm45/Makefile.inc | 2 ++ src/northbridge/intel/gm45/bootblock.c | 3 ++- src/northbridge/intel/gm45/romstage.c | 6 ------ 4 files changed, 5 insertions(+), 11 deletions(-) (limited to 'src/northbridge/intel/gm45') diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index 3042741370..e7bfe5d26a 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -26,15 +26,12 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select INTEL_GMA_ACPI select INTEL_GMA_SSC_ALTERNATE_REF select PARALLEL_MP + select C_ENVIRONMENT_BOOTBLOCK config CBFS_SIZE hex default 0x100000 -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/intel/gm45/bootblock.c" - config VGA_BIOS_ID string default "8086,2a42" diff --git a/src/northbridge/intel/gm45/Makefile.inc b/src/northbridge/intel/gm45/Makefile.inc index 3742cfcf7c..20fdbbe32c 100644 --- a/src/northbridge/intel/gm45/Makefile.inc +++ b/src/northbridge/intel/gm45/Makefile.inc @@ -15,6 +15,8 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_GM45),y) +bootblock-y += bootblock.c + romstage-y += early_init.c romstage-y += early_reset.c romstage-y += raminit.c diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c index c076c5506b..d3aeb030f1 100644 --- a/src/northbridge/intel/gm45/bootblock.c +++ b/src/northbridge/intel/gm45/bootblock.c @@ -11,13 +11,14 @@ * GNU General Public License for more details. */ +#include #include /* Just re-define these instead of including gm45.h. It blows up romcc. */ #define D0F0_PCIEXBAR_LO 0x60 #define D0F0_PCIEXBAR_HI 0x64 -static void bootblock_northbridge_init(void) +void bootblock_early_northbridge_init(void) { uint32_t reg; diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c index 7f45ca7f83..a146734158 100644 --- a/src/northbridge/intel/gm45/romstage.c +++ b/src/northbridge/intel/gm45/romstage.c @@ -62,12 +62,6 @@ void mainboard_romstage_entry(void) i82801ix_early_init(); setup_pch_gpios(&mainboard_gpio_map); - i82801ix_lpc_decode(); - - mb_setup_superio(); - - console_init(); - reg16 = pci_read_config16(LPC_DEV, D31F0_GEN_PMCON_3); pci_write_config16(LPC_DEV, D31F0_GEN_PMCON_3, reg16); if ((MCHBAR16(SSKPD_MCHBAR) == 0xCAFE) && !(reg16 & (1 << 9))) { -- cgit v1.2.3