From 3d45000c9cab2e5e5cac11a0a6af9abdce8aa80d Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 9 Aug 2018 18:55:58 +0200 Subject: src: Fix typo Change-Id: I689c5663ef59861f79b68220abd146144f7618de Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/27988 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/northbridge/intel/gm45/raminit.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/northbridge/intel/gm45') diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 08f954d057..03f617c6a3 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -869,7 +869,7 @@ static void configure_dram_control_mode(const timings_t *const timings, const di static void rcomp_initialization(const stepping_t stepping, const int sff) { - /* Programm RCOMP codes. */ + /* Program RCOMP codes. */ if (sff) die("SFF platform unsupported in RCOMP initialization.\n"); /* Values are for DDR3. */ @@ -1825,7 +1825,7 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) /* Some last optimizations. */ dram_optimizations(timings, dimms); - /* Mark raminit beeing finished. :-) */ + /* Mark raminit being finished. :-) */ u8 tmp8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2) & ~(1 << 7); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, tmp8); -- cgit v1.2.3