From aba8fb115802df289007ae9df3269d65cfd008c5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 2 Aug 2019 06:11:28 +0300 Subject: intel/i945,gm45,pineview,x4x: Move stage cache support function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Let garbage-collection take care of stage_cache_external_region() when it is not needed and move implementation to a suitable file already building for needed stages. Change-Id: Ic32adcc62c7ee21bf38e2e4e5ece00524871b091 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34670 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/gm45/ram_calc.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'src/northbridge/intel/gm45/ram_calc.c') diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index c6140824f0..719c59fbd4 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include "gm45.h" @@ -123,6 +124,17 @@ void *cbmem_top(void) return (void *) top_of_ram; } +void stage_cache_external_region(void **base, size_t *size) +{ + /* + * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. + * The top of RAM is defined to be the TSEG base address. + */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)(northbridge_get_tseg_base() + + CONFIG_SMM_RESERVED_SIZE); +} + /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ -- cgit v1.2.3