From 811932a61411f5258096e734a158be01c00cf940 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Fri, 22 Jul 2016 22:53:19 +0300 Subject: intel i945 gm45 x4x: Apply cbmem_top() alignment MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Force modest 4 MiB alignment to help with MTRR assignment. Change-Id: I49a7d1288bc079da1b8bd52150ddcfcfe2e51179 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/17780 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/northbridge/intel/gm45/ram_calc.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'src/northbridge/intel/gm45/ram_calc.c') diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index 146bcf2c7f..c22b491c66 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -82,9 +82,14 @@ static uintptr_t smm_region_start(void) return tor; } +/* Depending of UMA and TSEG configuration, TSEG might start at any + * 1 MiB aligment. As this may cause very greedy MTRR setup, push + * CBMEM top downwards to 4 MiB boundary. + */ void *cbmem_top(void) { - return (void *) smm_region_start(); + uintptr_t top_of_ram = ALIGN_DOWN(smm_region_start(), 4*MiB); + return (void *) top_of_ram; } void *setup_stack_and_mtrrs(void) -- cgit v1.2.3