From 12bed2608f2f98fd41f6dac9c918123f51e830d4 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 24 Nov 2016 13:23:05 +0100 Subject: nb/gm45/gma.c: Compute BLC_PWM_CTL value from PWM frequency This allows to set the backlight PWM frequency and the duty cycle in the devicetree instead of using a plain BLC_PWM_CTL value. Change-Id: I4d9a555ac7ea5605712c1fcda994a6fcabf9acf3 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/17597 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/northbridge/intel/gm45/gma.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) (limited to 'src/northbridge/intel/gm45/gma.c') diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 3e9f508b70..37f81c5094 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -629,11 +629,25 @@ static u32 get_cdclk(struct device *const dev) } } +static u32 freq_to_blc_pwm_ctl(struct device *const dev, + u16 pwm_freq, u8 duty_perc) +{ + u32 blc_mod; + + blc_mod = get_cdclk(dev) / (128 * pwm_freq); + + if (duty_perc <= 100) + return (blc_mod << 16) | (blc_mod * duty_perc / 100); + else + return (blc_mod << 16) | blc_mod; +} + static void gma_pm_init_post_vbios(struct device *const dev) { const struct northbridge_intel_gm45_config *const conf = dev->chip_info; u32 reg32; + u8 reg8; /* Setup Panel Power On Delays */ reg32 = gtt_read(PP_ON_DELAYS); @@ -661,10 +675,14 @@ static void gma_pm_init_post_vbios(struct device *const dev) /* Enable Backlight */ gtt_write(BLC_PWM_CTL2, (1 << 31)); - if (conf->gfx.backlight == 0) + reg8 = 100; + if (conf->duty_cycle != 0) + reg8 = conf->duty_cycle; + if (conf->pwm_freq == 0) gtt_write(BLC_PWM_CTL, 0x06100610); else - gtt_write(BLC_PWM_CTL, conf->gfx.backlight); + gtt_write(BLC_PWM_CTL, freq_to_blc_pwm_ctl(dev, + conf->pwm_freq, reg8)); } static void gma_func0_init(struct device *dev) -- cgit v1.2.3