From b053583a1c372a0b7018241a5e6bd2d8d00b843c Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 8 Jun 2020 11:46:58 +0200 Subject: nb/intel/gm45: Use PCI bitwise ops MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit While we are at it, also reflow a few lines that fit in 96 characters. Tested with BUILD_TIMELESS=1, Roda RK9 does not change. Change-Id: Icaca44280acdba099a5e13c5fd91d82c3e002bae Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/42189 Reviewed-by: Arthur Heymans Reviewed-by: Michael Niewöhner Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/northbridge/intel/gm45/early_reset.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'src/northbridge/intel/gm45/early_reset.c') diff --git a/src/northbridge/intel/gm45/early_reset.c b/src/northbridge/intel/gm45/early_reset.c index 44917465d6..17838809fa 100644 --- a/src/northbridge/intel/gm45/early_reset.c +++ b/src/northbridge/intel/gm45/early_reset.c @@ -40,12 +40,12 @@ void gm45_early_reset(void/*const timings_t *const timings*/) CxDRBy_BOUND_MB(r+1, 128); } /* Set DCC mode to no operation and do magic 0xf0 thing. */ - MCHBAR32(DCC_MCHBAR) = - (MCHBAR32(DCC_MCHBAR) & ~DCC_CMD_MASK) | DCC_CMD_NOP; - u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); - pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~(1 << 2)); - reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); - pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | (1 << 2)); + MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_CMD_MASK) | DCC_CMD_NOP; + + pci_and_config8(PCI_DEV(0, 0, 0), 0xf0, ~(1 << 2)); + + pci_or_config8(PCI_DEV(0, 0, 0), 0xf0, (1 << 2)); + /* Normally, we would set this after successful raminit. */ MCHBAR32(DCC_MCHBAR) |= (1 << 19); -- cgit v1.2.3