From 1ac6f8b804b0be461f5254a6bace3a9823177ba3 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 20 Jan 2021 13:13:26 +0100 Subject: nb/intel/gm45: Define and use MMCONF_BUS_NUMBER Change-Id: I635f3615f566502f79bbd81f9f743ce63bba3b1a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/49758 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/northbridge/intel/gm45/bootblock.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) (limited to 'src/northbridge/intel/gm45/bootblock.c') diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c index 2e41981e75..9c45f7e3f8 100644 --- a/src/northbridge/intel/gm45/bootblock.c +++ b/src/northbridge/intel/gm45/bootblock.c @@ -1,14 +1,24 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include +#include #include "gm45.h" -void bootblock_early_northbridge_init(void) +static uint32_t encode_pciexbar_length(void) { - uint32_t reg; + switch (CONFIG_MMCONF_BUS_NUMBER) { + case 256: return 0 << 1; + case 128: return 1 << 1; + case 64: return 2 << 1; + default: return dead_code_t(uint32_t); + } +} +void bootblock_early_northbridge_init(void) +{ /* * The "io" variant of the config access is explicitly used to * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to @@ -21,8 +31,7 @@ void bootblock_early_northbridge_init(void) * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. */ - reg = 0; - pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_HI, reg); - reg = CONFIG_MMCONF_BASE_ADDRESS | (2 << 1) | 1; /* 64MiB - 0-63 buses. */ - pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_LO, reg); + const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; + pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_HI, 0); + pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO, reg); } -- cgit v1.2.3