From a9a92ac961f8f46b7cdca2176428d5e363f44912 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 8 Jun 2023 15:22:27 +0200 Subject: acpi: Move ECAM resource below PNP0C02 device in a common place MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From the Linux documentation (Documentation/PCI/acpi-info.rst): [6] PCI Firmware 3.2, sec 4.1.2: If the operating system does not natively comprehend reserving the MMCFG region, the MMCFG region must be reserved by firmware. The address range reported in the MCFG table or by _CBA method (see Section 4.1.3) must be reserved by declaring a motherboard resource. For most systems, the motherboard resource would appear at the root of the ACPI namespace (under \_SB) in a node with a _HID of EISAID (PNP0C02), and the resources in this case should not be claimed in the root PCI bus’s _CRS. The resources can optionally be returned in Int15 E820 or EFIGetMemoryMap as reserved memory but must always be reported through ACPI as a motherboard resource. So in order for the OS to use ECAM MMCONF over legacy PCI IO configuration, a PNP0C02 HID device needs to reserve this region. As no AMD platform has this defined in DSDT this fixes Linux using legacy PCI IO configuration over MMCONF. Tianocore messes with e820 table in such a way that it prevents Linux from using PCIe ECAM. This change fixes that problem. Signed-off-by: Arthur Heymans Change-Id: I852e393726a1b086cf582f4d2d707e7cde05cbf4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75729 Reviewed-by: Felix Held Reviewed-by: Sean Rhodes Tested-by: build bot (Jenkins) --- src/northbridge/intel/gm45/acpi/gm45.asl | 1 - 1 file changed, 1 deletion(-) (limited to 'src/northbridge/intel/gm45/acpi') diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl index c4636beb3e..4e86092092 100644 --- a/src/northbridge/intel/gm45/acpi/gm45.asl +++ b/src/northbridge/intel/gm45/acpi/gm45.asl @@ -16,7 +16,6 @@ Device (PDRC) Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000) Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000) - Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH) Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH -- cgit v1.2.3