From e39becf5216419fa0a08c1d8632474fd8a9a5738 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Fri, 5 Jul 2019 18:05:17 +0300 Subject: intel/cpu: Switch older models to TSC_MONOTONIC_TIMER MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The implementation of udelay() with LAPIC timers existed first, as we did not have calculations implemented for TSC frequency. Change-Id: If510bcaadee67e3a5792b3fc7389353b672712f9 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34200 Reviewed-by: HAOUAS Elyes Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/northbridge/intel/fsp_rangeley/Makefile.inc | 2 - src/northbridge/intel/fsp_rangeley/udelay.c | 66 ------------------------- 2 files changed, 68 deletions(-) delete mode 100644 src/northbridge/intel/fsp_rangeley/udelay.c (limited to 'src/northbridge/intel/fsp_rangeley') diff --git a/src/northbridge/intel/fsp_rangeley/Makefile.inc b/src/northbridge/intel/fsp_rangeley/Makefile.inc index a2f80546d7..a167c2369e 100644 --- a/src/northbridge/intel/fsp_rangeley/Makefile.inc +++ b/src/northbridge/intel/fsp_rangeley/Makefile.inc @@ -27,8 +27,6 @@ romstage-y += memmap.c romstage-y += ../../../arch/x86/walkcbfs.S romstage-y += port_access.c -smm-y += udelay.c - CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR) CPPFLAGS_common += -I$(src)/northbridge/intel/fsp_rangeley/ diff --git a/src/northbridge/intel/fsp_rangeley/udelay.c b/src/northbridge/intel/fsp_rangeley/udelay.c deleted file mode 100644 index 08301a37f6..0000000000 --- a/src/northbridge/intel/fsp_rangeley/udelay.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -#define MSR_PLATFORM_INFO 0xce - -/** - * Intel Rangeley CPUs always run the TSC at BCLK = 100MHz - */ - -/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. - * This code is used to prevent use of libgcc's umoddi3. - */ -static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b) -{ - tsc->lo = (a & 0xffff) * (b & 0xffff); - tsc->hi = ((tsc->lo >> 16) - + ((a & 0xffff) * (b >> 16)) - + ((b & 0xffff) * (a >> 16))); - tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff); - tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16); -} - -void udelay(u32 us) -{ - u32 dword; - tsc_t tsc, tsc1, tscd; - msr_t msr; - u32 fsb = 100, divisor; - u32 d; /* ticks per us */ - - msr = rdmsr(MSR_PLATFORM_INFO); - divisor = (msr.lo >> 8) & 0xff; - - d = fsb * divisor; - multiply_to_tsc(&tscd, us, d); - - tsc1 = rdtsc(); - dword = tsc1.lo + tscd.lo; - if ((dword < tsc1.lo) || (dword < tscd.lo)) { - tsc1.hi++; - } - tsc1.lo = dword; - tsc1.hi += tscd.hi; - - do { - tsc = rdtsc(); - } while ((tsc.hi < tsc1.hi) - || ((tsc.hi == tsc1.hi) && (tsc.lo <= tsc1.lo))); -} -- cgit v1.2.3