From e119d86ca87937d45e67d00da722c28ac7ceaa9e Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Sat, 3 Aug 2019 21:28:40 +0300 Subject: intel/fsp_rangeley: Rename raminit.c to memmap.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use a name consistent with the more recent soc/intel. Change-Id: I704d7cb637e4e12039ade99f57e10af794c8be97 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34698 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: David Guckian --- src/northbridge/intel/fsp_rangeley/Makefile.inc | 4 +-- src/northbridge/intel/fsp_rangeley/memmap.c | 42 +++++++++++++++++++++++++ src/northbridge/intel/fsp_rangeley/raminit.c | 42 ------------------------- 3 files changed, 44 insertions(+), 44 deletions(-) create mode 100644 src/northbridge/intel/fsp_rangeley/memmap.c delete mode 100644 src/northbridge/intel/fsp_rangeley/raminit.c (limited to 'src/northbridge/intel/fsp_rangeley') diff --git a/src/northbridge/intel/fsp_rangeley/Makefile.inc b/src/northbridge/intel/fsp_rangeley/Makefile.inc index f9bf0507dc..a2f80546d7 100644 --- a/src/northbridge/intel/fsp_rangeley/Makefile.inc +++ b/src/northbridge/intel/fsp_rangeley/Makefile.inc @@ -18,12 +18,12 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_FSP_RANGELEY),y) subdirs-y += fsp ramstage-y += northbridge.c -ramstage-y += raminit.c +ramstage-y += memmap.c ramstage-y += acpi.c ramstage-y += port_access.c -romstage-y += raminit.c +romstage-y += memmap.c romstage-y += ../../../arch/x86/walkcbfs.S romstage-y += port_access.c diff --git a/src/northbridge/intel/fsp_rangeley/memmap.c b/src/northbridge/intel/fsp_rangeley/memmap.c new file mode 100644 index 0000000000..da9ed71a67 --- /dev/null +++ b/src/northbridge/intel/fsp_rangeley/memmap.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +#include "northbridge.h" + +static uintptr_t smm_region_start(void) +{ + /* + * Calculate the top of usable (low) DRAM. + * The FSP's reserved memory sits just below the SMM region, + * allowing calculation of the top of usable memory. + */ + uintptr_t tom = sideband_read(B_UNIT, BMBOUND); + uintptr_t bsmmrrl = sideband_read(B_UNIT, BSMMRRL) << 20; + if (bsmmrrl) { + tom = bsmmrrl; + } + + return tom; +} + +void *cbmem_top(void) +{ + return (void *) (smm_region_start() - FSP_RESERVE_MEMORY_SIZE); +} diff --git a/src/northbridge/intel/fsp_rangeley/raminit.c b/src/northbridge/intel/fsp_rangeley/raminit.c deleted file mode 100644 index da9ed71a67..0000000000 --- a/src/northbridge/intel/fsp_rangeley/raminit.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -#include "northbridge.h" - -static uintptr_t smm_region_start(void) -{ - /* - * Calculate the top of usable (low) DRAM. - * The FSP's reserved memory sits just below the SMM region, - * allowing calculation of the top of usable memory. - */ - uintptr_t tom = sideband_read(B_UNIT, BMBOUND); - uintptr_t bsmmrrl = sideband_read(B_UNIT, BSMMRRL) << 20; - if (bsmmrrl) { - tom = bsmmrrl; - } - - return tom; -} - -void *cbmem_top(void) -{ - return (void *) (smm_region_start() - FSP_RESERVE_MEMORY_SIZE); -} -- cgit v1.2.3