From 45022ae056cdbf58429b77daf2da176306312801 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <siro@das-labor.org>
Date: Mon, 1 Oct 2018 19:17:11 +0200
Subject: intel: Use CF9 reset (part 1)

Add SOUTHBRIDGE_INTEL_COMMON_RESET for all Intel platforms that used to
perform a "system reset" in their hard_reset() implementation. Replace
all duplicate CF9 reset implementations for these platforms.

Change-Id: I8e359b0c4d5a1060edd0940d24c2f78dfed8a590
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/northbridge/intel/fsp_rangeley')

diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
index 999d5a812e..fcba7c1457 100644
--- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
+++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
@@ -19,12 +19,12 @@
 #include <console/console.h>
 #include <bootstate.h>
 #include <cbmem.h>
+#include <cf9_reset.h>
 #include <device/device.h>
 #include <southbridge/intel/fsp_rangeley/pci_devs.h>
 #include <drivers/intel/fsp1_0/fsp_util.h>
 #include <fspvpd.h>
 #include <fspbootmode.h>
-#include <reset.h>
 #include "../chip.h"
 
 #ifdef __PRE_RAM__
@@ -173,7 +173,7 @@ void ChipsetFspReturnPoint(EFI_STATUS Status,
 	*(void **)CBMEM_FSP_HOB_PTR = HobListPtr;
 
 	if (Status == 0xFFFFFFFF) {
-		soft_reset();
+		system_reset();
 	}
 	romstage_main_continue(Status, HobListPtr);
 }
-- 
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