From 371e7d95aa640b4c815e71d2448f4c9b26c104bf Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Tue, 19 Jun 2018 17:53:50 +0300 Subject: nb/intel/e7505: Leave ROM as un-cacheable in postcar MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Collected timestamps indicate LZMA decompression of ramstage is 4x slower when ROM is marked WP-cacheable, in contrast to having ROM as US. A simple copy WP->WB with uncompressed ramstage also appeared to be twice as slow as UC->WB copy. It should be noted that if POSTCAR_STAGE was removed from build, un-lzma takes 130 seconds instead of 45 milliseconds. Change-Id: I2cf995395ef2d303ad0bc044dbfa160990a705d0 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/27164 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/e7505/memmap.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'src/northbridge/intel/e7505') diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c index 48527fdd96..1b86012907 100644 --- a/src/northbridge/intel/e7505/memmap.c +++ b/src/northbridge/intel/e7505/memmap.c @@ -48,9 +48,12 @@ void platform_enter_postcar(void) if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) die("Unable to initialize postcar frame.\n"); - /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, - MTRR_TYPE_WRPROT); + /* + * Choose to NOT set ROM as WP cacheable here. + * Timestamps indicate the CPU this northbridge code is + * connected to, performs better for memcpy() and un-lzma + * operations when source is left as UC. + */ /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); -- cgit v1.2.3