From 7b73e85283bea7f456ab2f86ed1d1099eb88bc2f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 8 Nov 2022 04:43:41 +0000 Subject: Revert "mb/aopen/dxplplusu: Remove board" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit eb76a455cd39ec59b7f2ba28baeec9538befd59e and applies minor fixes to make it build again. PARALLEL_MP was working prior to board removal and no relevant SMI handlers were implemented. So NO_SMM choice is now selected. Change-Id: Ia1cd02278240d1b5d006fb2a7730d3d86390f85b Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/69339 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/e7505/raminit.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 src/northbridge/intel/e7505/raminit.h (limited to 'src/northbridge/intel/e7505/raminit.h') diff --git a/src/northbridge/intel/e7505/raminit.h b/src/northbridge/intel/e7505/raminit.h new file mode 100644 index 0000000000..1e0128ce72 --- /dev/null +++ b/src/northbridge/intel/e7505/raminit.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef RAMINIT_H +#define RAMINIT_H + +#include + +#define MAX_DIMM_SOCKETS_PER_CHANNEL 4 +#define MAX_NUM_CHANNELS 2 +#define MAX_DIMM_SOCKETS (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL) + +struct mem_controller { + pci_devfn_t d0, d0f1; // PCI bus/device/fcns of E7501 memory controller + + // SMBus addresses of DIMM slots for each channel, + // in order from closest to MCH to furthest away + // 0 == not present + uint16_t channel0[MAX_DIMM_SOCKETS_PER_CHANNEL]; + uint16_t channel1[MAX_DIMM_SOCKETS_PER_CHANNEL]; +}; + +void sdram_initialize(void); + +#endif /* RAMINIT_H */ -- cgit v1.2.3