From 4c0e277e4ea358f7a36a75b503def54578fcd536 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Thu, 17 May 2018 14:16:03 +0300 Subject: intel/e7505: Assume AGP slot disabled MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reducing two AGP aperture windows from default 256 MiB to chipset minimum 4 MiB releases 504 MiB of unused MMIO space. Thus we can decrease MMIO space reserve from 1024 MiB to 512 MiB. Supported CPUs are 32-bit with PAE, so there is a little reason to avoid overlarge MMIO region. Change-Id: I34818e1ca36058309c7c5c295992ba6dda154acc Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/26758 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/northbridge/intel/e7505/e7505.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/northbridge/intel/e7505/e7505.h') diff --git a/src/northbridge/intel/e7505/e7505.h b/src/northbridge/intel/e7505/e7505.h index 9c9171d2bd..5ceeacceaf 100644 --- a/src/northbridge/intel/e7505/e7505.h +++ b/src/northbridge/intel/e7505/e7505.h @@ -42,6 +42,7 @@ #define DRC 0x7C /* DRAM Controller Mode register, 32 bit */ #define DRDCTL 0x80 /* DRAM Read Timing Control register, 16 bit? (if similar to 855PM) */ #define CKDIS 0x8C /* Clock disable register, 8 bit */ +#define APSIZE 0xB4 #define TOLM 0xC4 /* Top of Low Memory register, 16 bit */ #define REMAPBASE 0xC6 /* Remap Base Address register, 16 bit */ #define REMAPLIMIT 0xC8 /* Remap Limit Address register, 16 bit */ @@ -82,4 +83,8 @@ #define DRAM_FERR 0x80 /* DRAM first error register, 8 bits */ #define DRAM_NERR 0x82 /* DRAM next error register, 8 bits */ +/************ D1:F0 ************/ + +#define APSIZE1 0x74 + #endif /* NORTHBRIDGE_INTEL_E7505_E7505_H */ -- cgit v1.2.3