From 6ca7636c8f52560e732cdd5b1c7829cda5aa2bde Mon Sep 17 00:00:00 2001 From: "arch import user (historical)" Date: Wed, 6 Jul 2005 17:17:25 +0000 Subject: Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-51 Creator: Yinghai Lu cache_as_ram for AMD and some intel git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/northbridge/intel/e7501/northbridge.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/northbridge/intel/e7501/northbridge.c') diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c index 800831de3e..ff5763265a 100644 --- a/src/northbridge/intel/e7501/northbridge.c +++ b/src/northbridge/intel/e7501/northbridge.c @@ -15,6 +15,7 @@ static void pci_domain_read_resources(device_t dev) /* Initialize the system wide io space constraints */ resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + resource->base = 0x400; //yhlu resource->limit = 0xffffUL; resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; @@ -187,4 +188,5 @@ static void enable_dev(struct device *dev) struct chip_operations northbridge_intel_e7501_ops = { CHIP_NAME("Intel E7501 northbridge") + .enable_dev = enable_dev, }; -- cgit v1.2.3