From f8ee1806ac524bc782c93eccc59ee3c929abddb9 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Fri, 18 Jan 2008 15:08:58 +0000 Subject: Rename almost all occurences of LinuxBIOS to coreboot. Due to the automatic nature of this update, I am self-acking. It worked in abuild. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/northbridge/amd/amdfam10/amdfam10.h | 2 +- src/northbridge/amd/amdht/comlib.c | 4 ++-- src/northbridge/amd/amdht/comlib.h | 2 +- src/northbridge/amd/amdht/ht_wrapper.c | 2 +- src/northbridge/amd/amdk8/raminit_f_dqs.c | 2 +- src/northbridge/amd/amdmct/mct/mctmtr_d.c | 4 ++-- src/northbridge/amd/gx2/chipsetinit.c | 2 +- 7 files changed, 9 insertions(+), 9 deletions(-) (limited to 'src/northbridge/amd') diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index 029e5e7a6d..d3fb11e349 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -1019,7 +1019,7 @@ struct nodes_info_t { u32 up_planes; // down planes will be [up_planes, planes) } __attribute__((packed)); -/* be careful with the alignment of sysinfo, bacause sysinfo may be shared by linuxbios_car and linuxbios_ram stage. and linuxbios_ram may be running at 64bit later.*/ +/* be careful with the alignment of sysinfo, bacause sysinfo may be shared by coreboot_car and coreboot_ram stage. and coreboot_ram may be running at 64bit later.*/ #if CONFIG_AMDMCT == 0 //#define MEM_CS_COPY 1 diff --git a/src/northbridge/amd/amdht/comlib.c b/src/northbridge/amd/amdht/comlib.c index e9abb0bb06..249388b04a 100644 --- a/src/northbridge/amd/amdht/comlib.c +++ b/src/northbridge/amd/amdht/comlib.c @@ -206,14 +206,14 @@ u32 CALLCONV AmdRotateLeft(u32 value, u8 size, u32 count) void CALLCONV AmdPCIRead(SBDFO loc, u32 *Value) { - /* Use LinuxBIOS PCI functions */ + /* Use coreboot PCI functions */ *Value = pci_read_config32((loc & 0xFFFFF000), SBDFO_OFF(loc)); } void CALLCONV AmdPCIWrite(SBDFO loc, u32 *Value) { - /* Use LinuxBIOS PCI functions */ + /* Use coreboot PCI functions */ pci_write_config32((loc & 0xFFFFF000), SBDFO_OFF(loc), *Value); } diff --git a/src/northbridge/amd/amdht/comlib.h b/src/northbridge/amd/amdht/comlib.h index a8b7b5c1c9..1f6fc0f9fb 100644 --- a/src/northbridge/amd/amdht/comlib.h +++ b/src/northbridge/amd/amdht/comlib.h @@ -26,7 +26,7 @@ #include "porting.h" -/* include LinuxBIOS pci functions */ +/* include coreboot pci functions */ #include #include diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c index 09953da2c4..aaf67a47a7 100644 --- a/src/northbridge/amd/amdht/ht_wrapper.c +++ b/src/northbridge/amd/amdht/ht_wrapper.c @@ -124,7 +124,7 @@ void getAmdTopolist(u8 ***p) /** * void amd_ht_init(struct sys_info *sysinfo) * - * AMD HT init LinuxBIOS wrapper + * AMD HT init coreboot wrapper * */ void amd_ht_init(struct sys_info *sysinfo) diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index 757acba7d7..1b5af6864f 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -2003,7 +2003,7 @@ static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sy train_ram(nodeid, sysinfo, sysinfox); #else /* Can copy dqs_timing to ap cache and run from cache? - * we need linuxbios_ap_car.rom? and treat it as linuxbios_ram.rom for ap ? + * we need coreboot_ap_car.rom? and treat it as coreboot_ram.rom for ap ? */ copy_and_run_ap_code_in_car(retcall); // will go back by jump diff --git a/src/northbridge/amd/amdmct/mct/mctmtr_d.c b/src/northbridge/amd/amdmct/mct/mctmtr_d.c index c0839d2a88..d39bfcc8b2 100644 --- a/src/northbridge/amd/amdmct/mct/mctmtr_d.c +++ b/src/northbridge/amd/amdmct/mct/mctmtr_d.c @@ -75,7 +75,7 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, Set default values for CPU registers ======================================================================*/ - /* NOTE : For LinuxBIOS, we don't need to set mtrr enables here because + /* NOTE : For coreboot, we don't need to set mtrr enables here because they are still enable from cache_as_ram.inc */ addr = 0x250; @@ -88,7 +88,7 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, /*====================================================================== Set variable MTRR values ======================================================================*/ - /* NOTE: for LinuxBIOS change from 0x200 to 0x204: LinuxBIOS is using + /* NOTE: for coreboot change from 0x200 to 0x204: coreboot is using 0x200, 0x201 for [1M, CONFIG_TOP_MEM) 0x202, 0x203 for ROM Caching */ diff --git a/src/northbridge/amd/gx2/chipsetinit.c b/src/northbridge/amd/gx2/chipsetinit.c index dcbfdb99b6..4751886a45 100644 --- a/src/northbridge/amd/gx2/chipsetinit.c +++ b/src/northbridge/amd/gx2/chipsetinit.c @@ -295,7 +295,7 @@ chipsetinit (struct northbridge_amd_gx2_config *nb){ outb( P80_CHIPSET_INIT, 0x80); ChipsetGeodeLinkInit(); #if 0 - /* we hope NEVER to be in linuxbios when S3 resumes + /* we hope NEVER to be in coreboot when S3 resumes if (! IsS3Resume()) */ { struct acpiinit *aci = acpi_init_table; -- cgit v1.2.3