From db84a99011bef90c57fcbbd168c95ca6d7aceafd Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Tue, 24 Nov 2015 14:11:52 -0600 Subject: nb/amd/mct_ddr3: Properly set MR0 WR value The existing code accidentally truncated the MSB from the MR0 WR value. While this probably had a minimal effect in reality, it should be configured correctly for maximal system stability. Change-Id: Ifb8a39c6ca47b32b44d33735e5c6c39f1dc5a44e Signed-off-by: Timothy Pearson Reviewed-on: https://review.coreboot.org/13147 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand Reviewed-by: Felix Held Reviewed-by: Paul Menzel --- src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/northbridge/amd') diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c index 822d813ef1..bcf603139e 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c @@ -967,7 +967,7 @@ static u32 mct_MR0(struct MCTStatStruc *pMCTstat, /* Load data into MRS word */ ret |= (ppd & 0x1) << 12; - ret |= (wr_ap & 0x3) << 9; + ret |= (wr_ap & 0x7) << 9; ret |= (dll_reset & 0x1) << 8; ret |= (test_mode & 0x1) << 7; ret |= ((cas_latency & 0xe) >> 1) << 4; -- cgit v1.2.3