From c5d9e3b6dd2956a8864ab11ed89ddcff671b72c3 Mon Sep 17 00:00:00 2001 From: "arch import user (historical)" Date: Wed, 6 Jul 2005 17:17:37 +0000 Subject: Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-52 Creator: Yinghai Lu USE_DCACHE_RAM instead of CONFIG_DCACHE_RAM in raminit.c git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1968 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/northbridge/amd/amdk8/raminit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/northbridge/amd') diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index e34c93d5c7..5d9c320637 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -2308,7 +2308,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) 5. for node interleaving we need to set mem hole to every node ( need recalcute hole offset in f0 for every node) */ -#if CONFIG_DCACHE_RAM == 0 +#if USE_DCACHE_RAM == 0 /* Make certain the first 1M of memory is intialized */ print_debug("Clearing initial memory region: "); -- cgit v1.2.3