From bbd237702a0e6cc63d88308c6e164451f87300b4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 10 Jan 2019 05:41:23 +0200 Subject: binaryPI: Drop CONFIG_CBB and CONFIG_CDB MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Static values, copy paste from multi-node fam15 code. Add header that shall have declarations of functions common to different families factored out. Change-Id: I2401acb9269674bac054fa9a6dd60ca8a21b36a9 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/30731 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Nico Huber --- src/northbridge/amd/pi/00630F01/northbridge.c | 11 ++++++----- src/northbridge/amd/pi/00660F01/northbridge.c | 11 ++++++----- src/northbridge/amd/pi/00730F01/northbridge.c | 11 ++++++----- src/northbridge/amd/pi/nb_common.h | 19 +++++++++++++++++++ 4 files changed, 37 insertions(+), 15 deletions(-) create mode 100644 src/northbridge/amd/pi/nb_common.h (limited to 'src/northbridge/amd') diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 9ce811b315..d606dc5547 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER) #include @@ -102,7 +103,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi static struct device *get_node_pci(u32 nodeid, u32 fn) { - return pcidev_on_root(CONFIG_CDB + nodeid, fn); + return pcidev_on_root(DEV_CDB + nodeid, fn); } static void get_fx_devs(void) @@ -145,7 +146,7 @@ static void f1_write_config32(unsigned reg, u32 value) static u32 amdfam15_nodeid(struct device *dev) { - return (dev->path.pci.devfn >> 3) - CONFIG_CDB; + return (dev->path.pci.devfn >> 3) - DEV_CDB; } static void set_vga_enable_reg(u32 nodeid, u32 linkn) @@ -853,9 +854,9 @@ static void cpu_bus_scan(struct device *dev) printk(BIOS_SPEW, "KaveriPI Debug: AMD Topology Number of Modules (@0x%p) is %d\n", modules_ptr, modules); printk(BIOS_SPEW, "KaveriPI Debug: AMD Topology Number of IOAPICs (@0x%p) is %d\n", options, (int)(options->CfgPlatNumIoApics)); - dev_mc = pcidev_on_root(CONFIG_CDB, 0); + dev_mc = pcidev_on_root(DEV_CDB, 0); if (!dev_mc) { - printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB); + printk(BIOS_ERR, "0:%02x.0 not found", DEV_CDB); die(""); } sysconf_init(dev_mc); @@ -878,7 +879,7 @@ static void cpu_bus_scan(struct device *dev) unsigned devn; struct bus *pbus; - devn = CONFIG_CDB + i; + devn = DEV_CDB + i; pbus = dev_mc->bus; /* Find the cpu's pci device */ diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 696c6536ef..056e7012d9 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER) #include @@ -101,7 +102,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi static struct device *get_node_pci(u32 nodeid, u32 fn) { - return pcidev_on_root(CONFIG_CDB + nodeid, fn); + return pcidev_on_root(DEV_CDB + nodeid, fn); } static void get_fx_devs(void) @@ -144,7 +145,7 @@ static void f1_write_config32(unsigned reg, u32 value) static u32 amdfam15_nodeid(struct device *dev) { - return (dev->path.pci.devfn >> 3) - CONFIG_CDB; + return (dev->path.pci.devfn >> 3) - DEV_CDB; } static void set_vga_enable_reg(u32 nodeid, u32 linkn) @@ -843,9 +844,9 @@ static void cpu_bus_scan(struct device *dev) ioapic_count = (int)options->CfgPlatNumIoApics; ASSERT(ioapic_count > 0); - dev_mc = pcidev_on_root(CONFIG_CDB, 0); + dev_mc = pcidev_on_root(DEV_CDB, 0); if (!dev_mc) { - printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB); + printk(BIOS_ERR, "0:%02x.0 not found", DEV_CDB); die(""); } sysconf_init(dev_mc); @@ -868,7 +869,7 @@ static void cpu_bus_scan(struct device *dev) unsigned devn; struct bus *pbus; - devn = CONFIG_CDB + i; + devn = DEV_CDB + i; pbus = dev_mc->bus; /* Find the cpu's pci device */ diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index ebc1ca4037..2579d370a7 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -35,6 +35,7 @@ #include #include #include +#include #include #if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER) #include @@ -103,7 +104,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi static struct device *get_node_pci(u32 nodeid, u32 fn) { - return pcidev_on_root(CONFIG_CDB + nodeid, fn); + return pcidev_on_root(DEV_CDB + nodeid, fn); } static void get_fx_devs(void) @@ -146,7 +147,7 @@ static void f1_write_config32(unsigned reg, u32 value) static u32 amdfam16_nodeid(struct device *dev) { - return (dev->path.pci.devfn >> 3) - CONFIG_CDB; + return (dev->path.pci.devfn >> 3) - DEV_CDB; } static void set_vga_enable_reg(u32 nodeid, u32 linkn) @@ -1089,9 +1090,9 @@ static void cpu_bus_scan(struct device *dev) printk(BIOS_SPEW, "MullinsPI Debug: AMD Topology Number of Modules (@0x%p) is %d\n", modules_ptr, modules); printk(BIOS_SPEW, "MullinsPI Debug: AMD Topology Number of IOAPICs (@0x%p) is %d\n", options, (int)options->CfgPlatNumIoApics); - dev_mc = pcidev_on_root(CONFIG_CDB, 0); + dev_mc = pcidev_on_root(DEV_CDB, 0); if (!dev_mc) { - printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB); + printk(BIOS_ERR, "0:%02x.0 not found", DEV_CDB); die(""); } sysconf_init(dev_mc); @@ -1114,7 +1115,7 @@ static void cpu_bus_scan(struct device *dev) unsigned devn; struct bus *pbus; - devn = CONFIG_CDB + i; + devn = DEV_CDB + i; pbus = dev_mc->bus; /* Find the cpu's pci device */ diff --git a/src/northbridge/amd/pi/nb_common.h b/src/northbridge/amd/pi/nb_common.h new file mode 100644 index 0000000000..3e78155afd --- /dev/null +++ b/src/northbridge/amd/pi/nb_common.h @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AMD_NB_COMMON_H__ +#define __AMD_NB_COMMON_H__ + +#define DEV_CDB 0x18 + +#endif -- cgit v1.2.3