From b6fa61a1216cc48a199335d9414698401d20dbf2 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Fri, 20 Feb 2015 13:13:35 -0600 Subject: northbridge/amd/amdmct: Fix burst write depth on K10 rev. D and later MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The BKDG for K10 revision D and later processors recommends a smaller MCT burst write queue depth when using unganged memory. TEST: Booted ASUS KFSN4-DRE with both Opteron 8356 and Opteron 2431 processors. Change-Id: I36718d4972c9d2d0bdd3274191503b5fcd803f15 Signed-off-by: Timothy Pearson Reviewed-on: http://review.coreboot.org/8500 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Kyösti Mälkki --- src/northbridge/amd/amdmct/mct/mct_d.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'src/northbridge/amd') diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 7c7550d10b..bf832dad81 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson , Raptor Engineering * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -749,7 +750,12 @@ static void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat, } while (!(val & (1 << Dr_MemClrStatus))); } - val = 0x0FE40FC0; // BKDG recommended + /* Implement BKDG Rev 3.62 recommendations */ + val = 0x0FE40F80; + if (!(mctGetLogicalCPUID(0) & AMD_FAM10_LT_D) && mctGet_NVbits(NV_Unganged)) + val |= (0x18 << 2); + else + val |= (0x10 << 2); val |= MCCH_FlushWrOnStpGnt; // Set for S3 Set_NB32(dev, 0x11C, val); } -- cgit v1.2.3