From 65b72ab55d7dff1f13cdf495d345e04e634b97ac Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Mon, 5 Jan 2015 12:59:54 -0800 Subject: northbridge: Drop print_ implementation from non-romcc boards Because we had no stack on romcc boards, we had a separate, not as powerful clone of printk: print_*. Back in the day, like more than half a decade ago, we migrated a lot of boards to printk, but we never cleaned up the existing code to be consistent. instead, we worked around the problem with a very messy console.h (nowadays the mess is hidden in romstage_console.c and early_print.h) This patch cleans up the northbridge code to use printk() on all non-ROMCC boards. Change-Id: I4a36cd965c58aae65d74ce1e697dc0d0f58f47a1 Signed-off-by: Stefan Reinauer Reviewed-on: http://review.coreboot.org/7856 Reviewed-by: Edward O'Callaghan Tested-by: build bot (Jenkins) --- src/northbridge/amd/amdfam10/amdfam10.h | 7 +---- src/northbridge/amd/amdfam10/debug.c | 26 +++++++++--------- src/northbridge/amd/amdfam10/raminit_amdmct.c | 6 ++--- src/northbridge/amd/amdfam10/setup_resource_map.c | 20 +++++++------- src/northbridge/amd/amdk8/coherent_ht.c | 32 +++++++++++------------ src/northbridge/amd/amdk8/debug.c | 22 ++++++++-------- src/northbridge/amd/amdk8/f.h | 7 +---- src/northbridge/amd/amdk8/incoherent_ht.c | 10 +++---- src/northbridge/amd/amdk8/raminit_test.c | 29 +++++--------------- src/northbridge/amd/amdmct/mct/mct_d.c | 2 +- src/northbridge/amd/amdmct/mct/mctdqs_d.c | 14 +++++----- src/northbridge/amd/amdmct/mct/mctsrc.c | 20 +++++--------- src/northbridge/amd/amdmct/mct/mcttmrl.c | 7 ++--- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 14 +++++----- src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c | 7 ++--- src/northbridge/amd/gx2/raminit.c | 2 +- src/northbridge/amd/lx/raminit.c | 30 ++++++++++----------- 17 files changed, 105 insertions(+), 150 deletions(-) (limited to 'src/northbridge/amd') diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index d292306586..ab4b42e868 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -1147,11 +1147,7 @@ static void wait_all_core0_mem_trained(struct sys_info *sysinfo) } for(i=0; inodes; i++) { -#ifdef __PRE_RAM__ - print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\n"); -#else printk(BIOS_DEBUG, "mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]); -#endif switch(sysinfo->mem_trained[i]) { case 0: //don't need train case 1: //trained @@ -1164,11 +1160,10 @@ static void wait_all_core0_mem_trained(struct sys_info *sysinfo) } } if(needs_reset) { + printk(BIOS_DEBUG, "mem trained failed\n"); #ifdef __PRE_RAM__ - print_debug("mem trained failed\n"); soft_reset(); #else - printk(BIOS_DEBUG, "mem trained failed\n"); hard_reset(); #endif } diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c index 7d00af721e..d1fdaf832c 100644 --- a/src/northbridge/amd/amdfam10/debug.c +++ b/src/northbridge/amd/amdfam10/debug.c @@ -108,7 +108,7 @@ static void dump_pci_device_range(u32 dev, u32 start_reg, u32 size) val >>= 8; } } - print_debug("\n"); + printk(BIOS_DEBUG, "\n"); } static void dump_pci_device(u32 dev) @@ -122,7 +122,7 @@ static void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start, int i; int end = start + size; print_debug_pci_dev(dev); - print_debug(" -- index_reg="); print_debug_hex32(index_reg); + printk(BIOS_DEBUG, " -- index_reg=%08x", index_reg); for(i = start; i < end; i++) { u32 val; @@ -135,7 +135,7 @@ static void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start, } } - print_debug("\n"); + printk(BIOS_DEBUG, "\n"); } static inline void dump_pci_device_index_wait(u32 dev, u32 index_reg) @@ -151,7 +151,7 @@ static inline void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 l int i; print_debug_pci_dev(dev); - print_debug(" index reg: "); print_debug_hex16(index_reg); print_debug(" type: "); print_debug_hex8(type); + printk(BIOS_DEBUG, " index reg: %04x type: %02x", index_reg, type); type<<=28; @@ -163,7 +163,7 @@ static inline void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 l val = pci_read_config32_index(dev, index_reg, i|type); printk(BIOS_DEBUG, " %08x", val); } - print_debug("\n"); + printk(BIOS_DEBUG, "\n"); } static inline void dump_pci_devices(void) @@ -221,7 +221,7 @@ static inline void dump_pci_devices_on_bus(u32 busn) static void dump_spd_registers(const struct mem_controller *ctrl) { int i; - print_debug("\n"); + printk(BIOS_DEBUG, "\n"); for(i = 0; i < DIMM_SOCKETS; i++) { u32 device; device = ctrl->spd_addr[i]; @@ -241,7 +241,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl) byte = status & 0xff; printk(BIOS_DEBUG, "%02x ", byte); } - print_debug("\n"); + printk(BIOS_DEBUG, "\n"); } device = ctrl->spd_addr[i+DIMM_SOCKETS]; if (device) { @@ -260,14 +260,14 @@ static void dump_spd_registers(const struct mem_controller *ctrl) byte = status & 0xff; printk(BIOS_DEBUG, "%02x ", byte); } - print_debug("\n"); + printk(BIOS_DEBUG, "\n"); } } } static void dump_smbus_registers(void) { u32 device; - print_debug("\n"); + printk(BIOS_DEBUG, "\n"); for(device = 1; device < 0x80; device++) { int j; if( smbus_read_byte(device, 0) < 0 ) continue; @@ -285,7 +285,7 @@ static void dump_smbus_registers(void) byte = status & 0xff; printk(BIOS_DEBUG, "%02x ", byte); } - print_debug("\n"); + printk(BIOS_DEBUG, "\n"); } } #endif @@ -303,7 +303,7 @@ static inline void dump_io_resources(u32 port) val = inb(port); printk(BIOS_DEBUG, " %02x",val); if ((i & 0x0f) == 0x0f) { - print_debug("\n"); + printk(BIOS_DEBUG, "\n"); } port++; } @@ -312,12 +312,12 @@ static inline void dump_io_resources(u32 port) static inline void dump_mem(u32 start, u32 end) { u32 i; - print_debug("dump_mem:"); + printk(BIOS_DEBUG, "dump_mem:"); for(i=start;iMCTstat); struct DCTStatStruc *pDCTstatA = sysinfo->DCTstatA; - print_debug("raminit_amdmct begin:\n"); + printk(BIOS_DEBUG, "raminit_amdmct begin:\n"); mctAutoInitMCT_D(pMCTstat, pDCTstatA); - print_debug("raminit_amdmct end:\n"); + printk(BIOS_DEBUG, "raminit_amdmct end:\n"); } diff --git a/src/northbridge/amd/amdfam10/setup_resource_map.c b/src/northbridge/amd/amdfam10/setup_resource_map.c index 2eeca44bf7..ca7f96433c 100644 --- a/src/northbridge/amd/amdfam10/setup_resource_map.c +++ b/src/northbridge/amd/amdfam10/setup_resource_map.c @@ -23,7 +23,7 @@ static void setup_resource_map(const u32 *register_values, u32 max) { u32 i; -// print_debug("setting up resource map...."); +// printk(BIOS_DEBUG, "setting up resource map...."); for(i = 0; i < max; i += 3) { device_t dev; @@ -37,14 +37,14 @@ static void setup_resource_map(const u32 *register_values, u32 max) reg |= register_values[i+2]; pci_write_config32(dev, where, reg); } -// print_debug("done.\n"); +// printk(BIOS_DEBUG, "done.\n"); } void setup_resource_map_offset(const u32 *register_values, u32 max, u32 offset_pci_dev, u32 offset_io_base) { u32 i; -// print_debug("setting up resource map offset...."); +// printk(BIOS_DEBUG, "setting up resource map offset...."); for(i = 0; i < max; i += 3) { device_t dev; u32 where; @@ -56,7 +56,7 @@ void setup_resource_map_offset(const u32 *register_values, u32 max, u32 offset_p reg |= register_values[i+2] + offset_io_base; pci_write_config32(dev, where, reg); } -// print_debug("done.\n"); +// printk(BIOS_DEBUG, "done.\n"); } #define RES_PCI_IO 0x10 @@ -69,12 +69,12 @@ void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 offset u32 i; #if RES_DEBUG - print_debug("setting up resource map ex offset...."); + printk(BIOS_DEBUG, "setting up resource map ex offset...."); #endif #if RES_DEBUG - print_debug("\n"); + printk(BIOS_DEBUG, "\n"); #endif for(i = 0; i < max; i += 4) { #if RES_DEBUG @@ -127,7 +127,7 @@ void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 offset } #if RES_DEBUG - print_debug("done.\n"); + printk(BIOS_DEBUG, "done.\n"); #endif } @@ -136,11 +136,11 @@ void setup_resource_map_x(const u32 *register_values, u32 max) u32 i; #if RES_DEBUG - print_debug("setting up resource map ex offset...."); + printk(BIOS_DEBUG, "setting up resource map ex offset...."); #endif #if RES_DEBUG - print_debug("\n"); + printk(BIOS_DEBUG, "\n"); #endif for(i = 0; i < max; i += 4) { #if RES_DEBUG @@ -189,7 +189,7 @@ void setup_resource_map_x(const u32 *register_values, u32 max) } #if RES_DEBUG - print_debug("done.\n"); + printk(BIOS_DEBUG, "done.\n"); #endif } diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index 8abb31fad0..a8d87008f5 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -145,7 +145,7 @@ static void disable_probes(void) u32 val; - print_spew("Disabling read/write/fill probes for UP... "); + printk(BIOS_SPEW, "Disabling read/write/fill probes for UP... "); val=pci_read_config32(NODE_HT(0), HT_TRANSACTION_CONTROL); val |= HTTC_DIS_FILL_P | HTTC_DIS_RMT_MEM_C | HTTC_DIS_P_MEM_C | @@ -153,7 +153,7 @@ static void disable_probes(void) HTTC_DIS_RD_DW_P | HTTC_DIS_RD_B_P; pci_write_config32(NODE_HT(0), HT_TRANSACTION_CONTROL, val); - print_spew("done.\n"); + printk(BIOS_SPEW, "done.\n"); } @@ -199,14 +199,13 @@ static void enable_routing(u8 node) */ /* Enable routing table */ - print_spew("Enabling routing table for node "); - print_spew_hex8(node); + printk(BIOS_SPEW, "Enabling routing table for node %d", node); val=pci_read_config32(NODE_HT(node), 0x6c); val &= ~((1<<1)|(1<<0)); pci_write_config32(NODE_HT(node), 0x6c, val); - print_spew(" done.\n"); + printk(BIOS_SPEW, " done.\n"); } #if CONFIG_MAX_PHYSICAL_CPUS > 1 @@ -230,7 +229,7 @@ static u8 link_to_register(int ldt) if (ldt&0x02) return 0x00; /* we should never get here */ - print_spew("Unknown Link\n"); + printk(BIOS_SPEW, "Unknown Link\n"); return 0; } @@ -248,15 +247,14 @@ static void rename_temp_node(u8 node) { uint32_t val; - print_spew("Renaming current temporary node to "); - print_spew_hex8(node); + printk(BIOS_SPEW, "Renaming current temporary node to %d", node); val=pci_read_config32(NODE_HT(7), 0x60); val &= (~7); /* clear low bits. */ val |= node; /* new node */ pci_write_config32(NODE_HT(7), 0x60, val); - print_spew(" done.\n"); + printk(BIOS_SPEW, " done.\n"); } static int verify_connection(u8 dest) @@ -514,7 +512,7 @@ static void setup_remote_node(u8 node) }; int i; - print_spew("setup_remote_node: "); + printk(BIOS_SPEW, "setup_remote_node: "); /* copy the default resource map from node 0 */ for(i = 0; i < ARRAY_SIZE(pci_reg); i++) { @@ -525,7 +523,7 @@ static void setup_remote_node(u8 node) pci_write_config32(NODE_MP(7), reg, value); } - print_spew("done\n"); + printk(BIOS_SPEW, "done\n"); } #endif /* CONFIG_MAX_PHYSICAL_CPUS > 1*/ @@ -664,7 +662,7 @@ static void setup_remote_row_indirect_group(const u8 *conn, int num) static void setup_uniprocessor(void) { - print_spew("Enabling UP settings\n"); + printk(BIOS_SPEW, "Enabling UP settings\n"); #if CONFIG_LOGICAL_CPUS unsigned tmp = (pci_read_config32(NODE_MC(0), 0xe8) >> 12) & 3; if (tmp>0) return; @@ -1491,7 +1489,7 @@ static unsigned setup_smp(void) { unsigned nodes; - print_spew("Enabling SMP settings\n"); + printk(BIOS_SPEW, "Enabling SMP settings\n"); nodes = setup_smp2(); #if CONFIG_MAX_PHYSICAL_CPUS > 2 @@ -1528,14 +1526,14 @@ static unsigned verify_mp_capabilities(unsigned nodes) #if CONFIG_MAX_PHYSICAL_CPUS > 2 case 0x02: /* MPCap */ if(nodes > 2) { - print_err("Going back to DP\n"); + printk(BIOS_ERR, "Going back to DP\n"); return 2; } break; #endif case 0x00: /* Non SMP */ if(nodes >1 ) { - print_err("Going back to UP\n"); + printk(BIOS_ERR, "Going back to UP\n"); return 1; } break; @@ -1613,7 +1611,7 @@ static void coherent_ht_finalize(unsigned nodes) * registers on Hammer A0 revision. */ - print_spew("coherent_ht_finalize\n"); + printk(BIOS_SPEW, "coherent_ht_finalize\n"); #if !CONFIG_K8_REV_F_SUPPORT rev_a0 = is_cpu_rev_a0(); #endif @@ -1654,7 +1652,7 @@ static void coherent_ht_finalize(unsigned nodes) #endif } - print_spew("done\n"); + printk(BIOS_SPEW, "done\n"); } static int apply_cpu_errata_fixes(unsigned nodes) diff --git a/src/northbridge/amd/amdk8/debug.c b/src/northbridge/amd/amdk8/debug.c index 4f9d8cafa9..c1021e5736 100644 --- a/src/northbridge/amd/amdk8/debug.c +++ b/src/northbridge/amd/amdk8/debug.c @@ -54,7 +54,7 @@ static void dump_pci_device(unsigned dev) val = pci_read_config8(dev, i); printk(BIOS_DEBUG, " %02x", val); } - print_debug("\n"); + printk(BIOS_DEBUG, "\n"); } #if CONFIG_K8_REV_F_SUPPORT @@ -63,7 +63,7 @@ static inline void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg) { int i; print_debug_pci_dev(dev); - print_debug(" -- index_reg="); print_debug_hex32(index_reg); + printk(BIOS_DEBUG, " -- index_reg=%08x", index_reg); for(i = 0; i < 0x40; i++) { uint32_t val; @@ -76,7 +76,7 @@ static inline void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg) } } - print_debug("\n"); + printk(BIOS_DEBUG, "\n"); } #endif @@ -135,7 +135,7 @@ static inline void dump_pci_devices_on_bus(unsigned busn) static void dump_spd_registers(const struct mem_controller *ctrl) { int i; - print_debug("\n"); + printk(BIOS_DEBUG, "\n"); for(i = 0; i < 4; i++) { unsigned device; device = ctrl->channel0[i]; @@ -155,7 +155,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl) byte = status & 0xff; printk(BIOS_DEBUG, "%02x ", byte); } - print_debug("\n"); + printk(BIOS_DEBUG, "\n"); } device = ctrl->channel1[i]; if (device) { @@ -174,14 +174,14 @@ static void dump_spd_registers(const struct mem_controller *ctrl) byte = status & 0xff; printk(BIOS_DEBUG, "%02x ", byte); } - print_debug("\n"); + printk(BIOS_DEBUG, "\n"); } } } static void dump_smbus_registers(void) { unsigned device; - print_debug("\n"); + printk(BIOS_DEBUG, "\n"); for(device = 1; device < 0x80; device++) { int j; if( smbus_read_byte(device, 0) < 0 ) continue; @@ -199,7 +199,7 @@ static void dump_smbus_registers(void) byte = status & 0xff; printk(BIOS_DEBUG, "%02x ", byte); } - print_debug("\n"); + printk(BIOS_DEBUG, "\n"); } } #endif @@ -218,7 +218,7 @@ static inline void dump_io_resources(unsigned port) val = inb(port); printk(BIOS_DEBUG, " %02x",val); if ((i & 0x0f) == 0x0f) { - print_debug("\n"); + printk(BIOS_DEBUG, "\n"); } port++; } @@ -227,13 +227,13 @@ static inline void dump_io_resources(unsigned port) static inline void dump_mem(unsigned start, unsigned end) { unsigned i; - print_debug("dump_mem:"); + printk(BIOS_DEBUG, "dump_mem:"); for(i=start;inodes; i++) { -#ifdef __PRE_RAM__ - print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\n"); -#else printk(BIOS_DEBUG, "mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]); -#endif switch(sysinfo->mem_trained[i]) { case 0: //don't need train case 1: //trained @@ -581,11 +577,10 @@ static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo) } } if(needs_reset) { + printk(BIOS_DEBUG, "mem trained failed\n"); #ifdef __PRE_RAM__ - print_debug("mem trained failed\n"); soft_reset(); #else - printk(BIOS_DEBUG, "mem trained failed\n"); hard_reset(); #endif } diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c index cf8ad52fba..3c6cf33c9f 100644 --- a/src/northbridge/amd/amdk8/incoherent_ht.c +++ b/src/northbridge/amd/amdk8/incoherent_ht.c @@ -342,7 +342,7 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of pci_write_config16(udev, upos + LINK_CTRL(uoffs), ctrl); ctrl = pci_read_config16(udev, upos + LINK_CTRL(uoffs)); if (ctrl & ((1 << 4) | (1 << 8))) { - print_err("Detected error on Hypertransport Link\n"); + printk(BIOS_ERR, "Detected error on Hypertransport Link\n"); break; } } @@ -362,10 +362,10 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of pos = ht_lookup_slave_capability(dev); if (!pos) { - print_err("udev="); print_err_hex32(udev); - print_err("\tupos="); print_err_hex32(upos); - print_err("\tuoffs="); print_err_hex32(uoffs); - print_err("\tHT link capability not found\n"); + printk(BIOS_ERR, "udev=%08x", udev); + printk(BIOS_ERR, "\tupos=%08x", upos); + printk(BIOS_ERR, "\tuoffs=%08x", uoffs); + printk(BIOS_ERR, "\tHT link capability not found\n"); break; } diff --git a/src/northbridge/amd/amdk8/raminit_test.c b/src/northbridge/amd/amdk8/raminit_test.c index fd2107cce9..be46f27bca 100644 --- a/src/northbridge/amd/amdk8/raminit_test.c +++ b/src/northbridge/amd/amdk8/raminit_test.c @@ -57,11 +57,7 @@ static uint32_t pci_read_config32(device_t dev, unsigned where) (pci_register[addr + 3] << 24); #if 0 - print_debug("pcir32("); - print_debug_hex32(addr); - print_debug("):"); - print_debug_hex32(value); - print_debug("\n"); + printk(BIOS_DEBUG, "pcir32(%08x): %08x\n", addr, value); #endif return value; @@ -92,11 +88,7 @@ static void pci_write_config32(device_t dev, unsigned where, uint32_t value) pci_register[addr + 3] = (value >> 24) & 0xff; #if 0 - print_debug("pciw32("); - print_debug_hex32(addr); - print_debug(", "); - print_debug_hex32(value); - print_debug(")\n"); + printk(BIOS_DEBUG, "pciw32(%08x, %08x)\n", addr, value); #endif } @@ -285,13 +277,8 @@ static int spd_read_byte(unsigned device, unsigned address) } } #if 0 - print_debug("spd_read_byte("); - print_debug_hex32(device); - print_debug(", "); - print_debug_hex32(address); - print_debug(") -> "); - print_debug_hex32(result); - print_debug("\n"); + printk(BIOS_DEBUG, "spd_read_byte(%08x, %08x) -> %08x\n", + device, address, result); #endif if (spd_count >= spd_fail_count) { result = -1; @@ -392,9 +379,7 @@ static void test1(void) raminit_main(); #if 0 - print_debug("spd_count: "); - print_debug_hex32(spd_count); - print_debug("\n"); + printk(BIOS_DEBUG, "spd_count: %d\n", spd_count); #endif } @@ -410,9 +395,7 @@ static void do_test2(int i) reset_tests(); spd_fail_count = i; - print_debug("\nSPD will fail after: "); - print_debug_hex32(spd_fail_count); - print_debug(" accesses.\n"); + printk(BIOS_DEBUG, "\nSPD will fail after: %d accesses.\n", %d); memcpy(&spd_data[0*256], spd_micron_512MB_DDR333, 256); memcpy(&spd_data[1*256], spd_micron_512MB_DDR333, 256); diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 924c5fb645..7c7550d10b 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -262,7 +262,7 @@ restartinit: node_sys_base += (pDCTstat->NodeSysLimit + 2) & ~0x0F; } if (NodesWmem == 0) { - print_debug("No Nodes?!\n"); + printk(BIOS_DEBUG, "No Nodes?!\n"); goto fatalexit; } diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c index 17fb289268..d7fd7383ca 100644 --- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c @@ -357,22 +357,20 @@ static void TrainDQSRdWrPos_D(struct MCTStatStruc *pMCTstat, for (Dir = 0; Dir < 2; Dir++) { if (Dir == 0) { - print_debug("TrainDQSRdWrPos: CH_D_DIR_B_DQS WR:\n"); + printk(BIOS_DEBUG, "TrainDQSRdWrPos: CH_D_DIR_B_DQS WR:\n"); } else { - print_debug("TrainDQSRdWrPos: CH_D_DIR_B_DQS RD:\n"); + printk(BIOS_DEBUG, "TrainDQSRdWrPos: CH_D_DIR_B_DQS RD:\n"); } for (Channel = 0; Channel < 2; Channel++) { - print_debug("Channel:"); print_debug_hex8(Channel); print_debug("\n"); + printk(BIOS_DEBUG, "Channel: %02x\n", Channel); for (Receiver = cs_start; Receiver < (cs_start + 2); Receiver += 2) { - print_debug("\t\tReceiver:"); print_debug_hex8(Receiver); + printk(BIOS_DEBUG, "\t\tReceiver: %02x: ", Receiver); p = pDCTstat->CH_D_DIR_B_DQS[Channel][Receiver >> 1][Dir]; - print_debug(": "); for (i=0;i<8; i++) { val = p[i]; - print_debug_hex8(val); - print_debug(" "); + printk(BIOS_DEBUG, "%02x ", val); } - print_debug("\n"); + printk(BIOS_DEBUG, "\n"); } } } diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c index feb41704d0..9c1324dd45 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc.c @@ -459,12 +459,9 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, #if DQS_TRAIN_DEBUG > 0 { u8 Channel; - print_debug("TrainRcvrEn: CH_MaxRdLat:\n"); + printk(BIOS_DEBUG, "TrainRcvrEn: CH_MaxRdLat:\n"); for(Channel = 0; Channel<2; Channel++) { - print_debug("Channel:"); print_debug_hex8(Channel); - print_debug(": "); - print_debug_hex8( pDCTstat->CH_MaxRdLat[Channel] ); - print_debug("\n"); + printk(BIOS_DEBUG, "Channel: %02x: %02x\n", Channel, pDCTstat->CH_MaxRdLat[Channel]); } } #endif @@ -476,20 +473,17 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, u8 i; u8 *p; - print_debug("TrainRcvrEn: CH_D_B_RCVRDLY:\n"); + printk(BIOS_DEBUG, "TrainRcvrEn: CH_D_B_RCVRDLY:\n"); for(Channel = 0; Channel < 2; Channel++) { - print_debug("Channel:"); print_debug_hex8(Channel); print_debug("\n"); + printk(BIOS_DEBUG, "Channel: %02x\n", Channel); for(Receiver = 0; Receiver<8; Receiver+=2) { - print_debug("\t\tReceiver:"); - print_debug_hex8(Receiver); + printk(BIOS_DEBUG, "\t\tReceiver: %02x: ", Receiver); p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1]; - print_debug(": "); for (i=0;i<8; i++) { val = p[i]; - print_debug_hex8(val); - print_debug(" "); + printk(BIOS_DEBUG, "%02x ", val); } - print_debug("\n"); + printk(BIOS_DEBUG, "\n"); } } } diff --git a/src/northbridge/amd/amdmct/mct/mcttmrl.c b/src/northbridge/amd/amdmct/mct/mcttmrl.c index 03ebf97c82..d31e7447a7 100644 --- a/src/northbridge/amd/amdmct/mct/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct/mcttmrl.c @@ -198,12 +198,9 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, #if DQS_TRAIN_DEBUG > 0 { u8 Channel; - print_debug("maxRdLatencyTrain: CH_MaxRdLat:\n"); + printk(BIOS_DEBUG, "maxRdLatencyTrain: CH_MaxRdLat:\n"); for(Channel = 0; Channel<2; Channel++) { - print_debug("Channel:"); print_debug_hex8(Channel); - print_debug(": "); - print_debug_hex8( pDCTstat->CH_MaxRdLat[Channel] ); - print_debug("\n"); + printk(BIOS_DEBUG, "Channel: %02x: %02x\n", Channel, pDCTstat->CH_MaxRdLat[Channel]); } } #endif diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index d7084ad385..6a9b921693 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -371,22 +371,20 @@ static void TrainDQSRdWrPos_D(struct MCTStatStruc *pMCTstat, for (Dir = 0; Dir < 2; Dir++) { if (Dir == 1) { - print_debug("TrainDQSRdWrPos: CH_D_DIR_B_DQS WR:\n"); + printk(BIOS_DEBUG, "TrainDQSRdWrPos: CH_D_DIR_B_DQS WR:\n"); } else { - print_debug("TrainDQSRdWrPos: CH_D_DIR_B_DQS RD:\n"); + printk(BIOS_DEBUG, "TrainDQSRdWrPos: CH_D_DIR_B_DQS RD:\n"); } for (Channel = 0; Channel < 2; Channel++) { - print_debug("Channel:"); print_debug_hex8(Channel); print_debug("\n"); + printk(BIOS_DEBUG, "Channel: %02x\n", Channel); for (Receiver = cs_start; Receiver < (cs_start + 2); Receiver += 2) { - print_debug("\t\tReceiver:"); print_debug_hex8(Receiver); + printk(BIOS_DEBUG, "\t\tReceiver: %02x: ", Receiver); p = pDCTstat->CH_D_DIR_B_DQS[Channel][Receiver >> 1][Dir]; - print_debug(": "); for (i=0;i<8; i++) { val = p[i]; - print_debug_hex8(val); - print_debug(" "); + printk(BIOS_DEBUG, "%02x ", val); } - print_debug("\n"); + printk(BIOS_DEBUG, "\n"); } } } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c index c7e135291d..ec8df9a8b8 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c @@ -192,12 +192,9 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, #if DQS_TRAIN_DEBUG > 0 { u8 Channel; - print_debug("maxRdLatencyTrain: CH_MaxRdLat:\n"); + printk(BIOS_DEBUG, "maxRdLatencyTrain: CH_MaxRdLat:\n"); for(Channel = 0; Channel<2; Channel++) { - print_debug("Channel:"); print_debug_hex8(Channel); - print_debug(": "); - print_debug_hex8( pDCTstat->CH_MaxRdLat[Channel] ); - print_debug("\n"); + printk(BIOS_DEBUG, "Channel: %02x: %02x\n", Channel, pDCTstat->CH_MaxRdLat[Channel]); } } #endif diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c index d9af16108f..fd872b346f 100644 --- a/src/northbridge/amd/gx2/raminit.c +++ b/src/northbridge/amd/gx2/raminit.c @@ -606,6 +606,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) *ptr = (unsigned long)i; } - print_info("RAM DLL lock\n"); + printk(BIOS_INFO, "RAM DLL lock\n"); } diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c index 7c95ab4bd2..d8515c645e 100644 --- a/src/northbridge/amd/lx/raminit.c +++ b/src/northbridge/amd/lx/raminit.c @@ -38,13 +38,13 @@ static void banner(const char *s) static void __attribute__((noreturn)) hcf(void) { - print_emerg("DIE\n"); + printk(BIOS_EMERG, "DIE\n"); /* this guarantees we flush the UART fifos (if any) and also * ensures that things, in general, keep going so no debug output * is lost */ while (1) - print_emerg_char(0); + printk(BIOS_EMERG, "%c", 0); } static void auto_size_dimm(unsigned int dimm) @@ -67,7 +67,7 @@ static void auto_size_dimm(unsigned int dimm) /* EEPROM byte usage: (5) Number of DIMM Banks */ spd_byte = spd_read_byte(dimm, SPD_NUM_DIMM_BANKS); if ((MIN_MOD_BANKS > spd_byte) || (spd_byte > MAX_MOD_BANKS)) { - print_emerg("Number of module banks not compatible\n"); + printk(BIOS_EMERG, "Number of module banks not compatible\n"); post_code(ERROR_BANK_SET); hcf(); } @@ -78,7 +78,7 @@ static void auto_size_dimm(unsigned int dimm) /* EEPROM byte usage: (17) Number of Banks on SDRAM Device */ spd_byte = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM); if ((MIN_DEV_BANKS > spd_byte) || (spd_byte > MAX_DEV_BANKS)) { - print_emerg("Number of device banks not compatible\n"); + printk(BIOS_EMERG, "Number of device banks not compatible\n"); post_code(ERROR_BANK_SET); hcf(); } @@ -94,7 +94,7 @@ static void auto_size_dimm(unsigned int dimm) */ if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0) || (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) { - print_emerg("Assymetirc DIMM not compatible\n"); + printk(BIOS_EMERG, "Assymetirc DIMM not compatible\n"); post_code(ERROR_UNSUPPORTED_DIMM); hcf(); } @@ -111,7 +111,7 @@ static void auto_size_dimm(unsigned int dimm) dimm_size = __builtin_ctz(dimm_size); banner("TEST DIMM SIZE>8"); if (dimm_size > 8) { /* 8 is 1GB only support 1GB per DIMM */ - print_emerg("Only support up to 1 GB per DIMM\n"); + printk(BIOS_EMERG, "Only support up to 1 GB per DIMM\n"); post_code(ERROR_DENSITY_DIMM); hcf(); } @@ -144,7 +144,7 @@ static void auto_size_dimm(unsigned int dimm) spd_byte = NumColAddr[spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF]; banner("MAXCOLADDR"); if (spd_byte > MAX_COL_ADDR) { - print_emerg("DIMM page size not compatible\n"); + printk(BIOS_EMERG, "DIMM page size not compatible\n"); post_code(ERROR_SET_PAGE); hcf(); } @@ -186,7 +186,7 @@ static void checkDDRMax(void) /* I don't think you need this check. if (spd_byte0 >= 0xA0 || spd_byte1 >= 0xA0){ - print_emerg("DIMM overclocked. Check GeodeLink Speed\n"); + printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink Speed\n"); post_code(POST_PLL_MEM_FAIL); hcf(); } */ @@ -201,7 +201,7 @@ static void checkDDRMax(void) /* current speed > max speed? */ if (GeodeLinkSpeed() > speed) { - print_emerg("DIMM overclocked. Check GeodeLink Speed\n"); + printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink Speed\n"); post_code(POST_PLL_MEM_FAIL); hcf(); } @@ -319,7 +319,7 @@ static void setCAS(void) } else if ((casmap0 &= casmap1)) { spd_byte = CASDDR[__builtin_ctz(casmap0)]; } else { - print_emerg("DIMM CAS Latencies not compatible\n"); + printk(BIOS_EMERG, "DIMM CAS Latencies not compatible\n"); post_code(ERROR_DIFF_DIMMS); hcf(); } @@ -513,7 +513,7 @@ static void EnableMTest(void) msr.lo |= CFCLK_LOWER_TRISTATE_DIS_SET; wrmsr(MC_CFCLK_DBUG, msr); - print_info("Enabled MTest for TLA debug\n"); + printk(BIOS_INFO, "Enabled MTest for TLA debug\n"); } #endif @@ -558,14 +558,14 @@ void sdram_set_spd_registers(const struct mem_controller *ctrl) banner("Check DIMM 0"); /* Check DIMM is not Register and not Buffered DIMMs. */ if ((spd_byte != 0xFF) && (spd_byte & 3)) { - print_emerg("DIMM0 NOT COMPATIBLE\n"); + printk(BIOS_EMERG, "DIMM0 NOT COMPATIBLE\n"); post_code(ERROR_UNSUPPORTED_DIMM); hcf(); } banner("Check DIMM 1"); spd_byte = spd_read_byte(DIMM1, SPD_MODULE_ATTRIBUTES); if ((spd_byte != 0xFF) && (spd_byte & 3)) { - print_emerg("DIMM1 NOT COMPATIBLE\n"); + printk(BIOS_EMERG, "DIMM1 NOT COMPATIBLE\n"); post_code(ERROR_UNSUPPORTED_DIMM); hcf(); } @@ -633,7 +633,7 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl) msr = rdmsr(MC_CF07_DATA); if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) == ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) { - print_emerg("No memory in the system\n"); + printk(BIOS_EMERG, "No memory in the system\n"); post_code(ERROR_NO_DIMMS); hcf(); } @@ -775,6 +775,6 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl) msr.lo |= 1; wrmsr(msrnum, msr); } - print_info("RAM DLL lock\n"); + printk(BIOS_INFO, "RAM DLL lock\n"); } -- cgit v1.2.3