From 64ed2b73451de4b655b3fdda0ff42825a165c317 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Wed, 31 Mar 2010 14:47:43 +0000 Subject: Drop \r\n and \n\r as both print_XXX and printk now do this internally. Only some assembler files still have \r\n ... Can we move that part to C completely? Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/northbridge/amd/amdk8/amdk8_f.h | 4 +-- src/northbridge/amd/amdk8/coherent_ht.c | 24 +++++++-------- src/northbridge/amd/amdk8/incoherent_ht.c | 42 +++++++++++++------------- src/northbridge/amd/amdk8/northbridge.c | 2 +- src/northbridge/amd/amdk8/raminit_f_dqs.c | 36 +++++++++++----------- src/northbridge/amd/amdk8/raminit_test.c | 6 ++-- src/northbridge/amd/amdk8/setup_resource_map.c | 24 +++++++-------- src/northbridge/amd/gx1/raminit.c | 32 ++++++++++---------- src/northbridge/amd/gx2/pll_reset.c | 10 +++--- src/northbridge/amd/gx2/raminit.c | 16 +++++----- src/northbridge/amd/lx/pll_reset.c | 2 +- src/northbridge/amd/lx/raminit.c | 14 ++++----- 12 files changed, 106 insertions(+), 106 deletions(-) (limited to 'src/northbridge/amd') diff --git a/src/northbridge/amd/amdk8/amdk8_f.h b/src/northbridge/amd/amdk8/amdk8_f.h index ea4e8947f8..8b1b0a0af1 100644 --- a/src/northbridge/amd/amdk8/amdk8_f.h +++ b/src/northbridge/amd/amdk8/amdk8_f.h @@ -559,7 +559,7 @@ static void wait_all_core0_mem_trained(struct sys_info *sysinfo) for(i=0; inodes; i++) { #ifdef __PRE_RAM__ - print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\r\n"); + print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\n"); #else printk(BIOS_DEBUG, "mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]); #endif @@ -576,7 +576,7 @@ static void wait_all_core0_mem_trained(struct sys_info *sysinfo) } if(needs_reset) { #ifdef __PRE_RAM__ - print_debug("mem trained failed\r\n"); + print_debug("mem trained failed\n"); soft_reset(); #else printk(BIOS_DEBUG, "mem trained failed\n"); diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index 66876c2148..39182854eb 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -111,7 +111,7 @@ static inline void print_linkn (const char *strval, uint8_t byteval) { - printk(BIOS_DEBUG, "%s%02x\r\n", strval, byteval); + printk(BIOS_DEBUG, "%s%02x\n", strval, byteval); } static void disable_probes(void) @@ -149,7 +149,7 @@ static void disable_probes(void) HTTC_DIS_RD_DW_P | HTTC_DIS_RD_B_P; pci_write_config32(NODE_HT(0), HT_TRANSACTION_CONTROL, val); - print_spew("done.\r\n"); + print_spew("done.\n"); } @@ -200,7 +200,7 @@ static void enable_routing(u8 node) val &= ~((1<<1)|(1<<0)); pci_write_config32(NODE_HT(node), 0x6c, val); - print_spew(" done.\r\n"); + print_spew(" done.\n"); } static void fill_row(u8 node, u8 row, u32 value) @@ -250,7 +250,7 @@ static void rename_temp_node(u8 node) val |= node; /* new node */ pci_write_config32(NODE_HT(7), 0x60, val); - print_spew(" done.\r\n"); + print_spew(" done.\n"); } static int verify_connection(u8 dest) @@ -513,7 +513,7 @@ static void setup_remote_node(u8 node) pci_write_config32(NODE_MP(7), reg, value); } - print_spew("done\r\n"); + print_spew("done\n"); } #endif /* CONFIG_MAX_PHYSICAL_CPUS > 1*/ @@ -652,7 +652,7 @@ static void setup_remote_row_indirect_group(const u8 *conn, int num) static void setup_uniprocessor(void) { - print_spew("Enabling UP settings\r\n"); + print_spew("Enabling UP settings\n"); #if CONFIG_LOGICAL_CPUS==1 unsigned tmp = (pci_read_config32(NODE_MC(0), 0xe8) >> 12) & 3; if (tmp>0) return; @@ -1478,7 +1478,7 @@ static unsigned setup_smp(void) { unsigned nodes; - print_spew("Enabling SMP settings\r\n"); + print_spew("Enabling SMP settings\n"); nodes = setup_smp2(); #if CONFIG_MAX_PHYSICAL_CPUS > 2 @@ -1496,7 +1496,7 @@ static unsigned setup_smp(void) nodes = setup_smp8(); #endif - printk(BIOS_DEBUG, "%02x nodes initialized.\r\n", nodes); + printk(BIOS_DEBUG, "%02x nodes initialized.\n", nodes); return nodes; } @@ -1515,14 +1515,14 @@ static unsigned verify_mp_capabilities(unsigned nodes) #if CONFIG_MAX_PHYSICAL_CPUS > 2 case 0x02: /* MPCap */ if(nodes > 2) { - print_err("Going back to DP\r\n"); + print_err("Going back to DP\n"); return 2; } break; #endif case 0x00: /* Non SMP */ if(nodes >1 ) { - print_err("Going back to UP\r\n"); + print_err("Going back to UP\n"); return 1; } break; @@ -1601,7 +1601,7 @@ static void coherent_ht_finalize(unsigned nodes) * registers on Hammer A0 revision. */ - print_spew("coherent_ht_finalize\r\n"); + print_spew("coherent_ht_finalize\n"); #if CONFIG_K8_REV_F_SUPPORT == 0 rev_a0 = is_cpu_rev_a0(); #endif @@ -1642,7 +1642,7 @@ static void coherent_ht_finalize(unsigned nodes) #endif } - print_spew("done\r\n"); + print_spew("done\n"); } static int apply_cpu_errata_fixes(unsigned nodes) diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c index 2e68618100..6a85516211 100644 --- a/src/northbridge/amd/amdk8/incoherent_ht.c +++ b/src/northbridge/amd/amdk8/incoherent_ht.c @@ -26,7 +26,7 @@ static inline void print_linkn_in (const char *strval, uint8_t byteval) { - printk(BIOS_DEBUG, "%s%02x\r\n", strval, byteval); + printk(BIOS_DEBUG, "%s%02x\n", strval, byteval); } static uint8_t ht_lookup_capability(device_t dev, uint16_t val) @@ -127,7 +127,7 @@ static uint16_t ht_read_freq_cap(device_t dev, uint8_t pos) uint32_t id; freq_cap = pci_read_config16(dev, pos); - printk(BIOS_SPEW, "pos=0x%x, unfiltered freq_cap=0x%x\r\n", pos, freq_cap); + printk(BIOS_SPEW, "pos=0x%x, unfiltered freq_cap=0x%x\n", pos, freq_cap); freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */ id = pci_read_config32(dev, 0); @@ -157,8 +157,8 @@ static uint16_t ht_read_freq_cap(device_t dev, uint8_t pos) #endif } - printk(BIOS_SPEW, "pos=0x%x, filtered freq_cap=0x%x\r\n", pos, freq_cap); - //printk(BIOS_SPEW, "capping to 800/600/400/200 MHz\r\n"); + printk(BIOS_SPEW, "pos=0x%x, filtered freq_cap=0x%x\n", pos, freq_cap); + //printk(BIOS_SPEW, "capping to 800/600/400/200 MHz\n"); //freq_cap &= 0x3f; return freq_cap; } @@ -220,14 +220,14 @@ static int ht_optimize_link( int needs_reset; /* Set link width and frequency */ - printk(BIOS_SPEW, "entering ht_optimize_link\r\n"); + printk(BIOS_SPEW, "entering ht_optimize_link\n"); /* Initially assume everything is already optimized and I don't need a reset */ needs_reset = 0; /* Get the frequency capabilities */ freq_cap1 = ht_read_freq_cap(dev1, pos1 + LINK_FREQ_CAP(offs1)); freq_cap2 = ht_read_freq_cap(dev2, pos2 + LINK_FREQ_CAP(offs2)); - printk(BIOS_SPEW, "freq_cap1=0x%x, freq_cap2=0x%x\r\n", freq_cap1, freq_cap2); + printk(BIOS_SPEW, "freq_cap1=0x%x, freq_cap2=0x%x\n", freq_cap1, freq_cap2); /* Calculate the highest possible frequency */ freq = log2(freq_cap1 & freq_cap2); @@ -236,11 +236,11 @@ static int ht_optimize_link( old_freq = pci_read_config8(dev1, pos1 + LINK_FREQ(offs1)); old_freq &= 0x0f; needs_reset |= old_freq != freq; - printk(BIOS_SPEW, "dev1 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\r\n", old_freq, freq, needs_reset); + printk(BIOS_SPEW, "dev1 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\n", old_freq, freq, needs_reset); old_freq = pci_read_config8(dev2, pos2 + LINK_FREQ(offs2)); old_freq &= 0x0f; needs_reset |= old_freq != freq; - printk(BIOS_SPEW, "dev2 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\r\n", old_freq, freq, needs_reset); + printk(BIOS_SPEW, "dev2 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\n", old_freq, freq, needs_reset); /* Set the Calculated link frequency */ pci_write_config8(dev1, pos1 + LINK_FREQ(offs1), freq); @@ -249,45 +249,45 @@ static int ht_optimize_link( /* Get the width capabilities */ width_cap1 = ht_read_width_cap(dev1, pos1 + LINK_WIDTH(offs1)); width_cap2 = ht_read_width_cap(dev2, pos2 + LINK_WIDTH(offs2)); - printk(BIOS_SPEW, "width_cap1=0x%x, width_cap2=0x%x\r\n", width_cap1, width_cap2); + printk(BIOS_SPEW, "width_cap1=0x%x, width_cap2=0x%x\n", width_cap1, width_cap2); /* Calculate dev1's input width */ ln_width1 = link_width_to_pow2[width_cap1 & 7]; ln_width2 = link_width_to_pow2[(width_cap2 >> 4) & 7]; - printk(BIOS_SPEW, "dev1 input ln_width1=0x%x, ln_width2=0x%x\r\n", ln_width1, ln_width2); + printk(BIOS_SPEW, "dev1 input ln_width1=0x%x, ln_width2=0x%x\n", ln_width1, ln_width2); if (ln_width1 > ln_width2) { ln_width1 = ln_width2; } width = pow2_to_link_width[ln_width1]; - printk(BIOS_SPEW, "dev1 input width=0x%x\r\n", width); + printk(BIOS_SPEW, "dev1 input width=0x%x\n", width); /* Calculate dev1's output width */ ln_width1 = link_width_to_pow2[(width_cap1 >> 4) & 7]; ln_width2 = link_width_to_pow2[width_cap2 & 7]; - printk(BIOS_SPEW, "dev1 output ln_width1=0x%x, ln_width2=0x%x\r\n", ln_width1, ln_width2); + printk(BIOS_SPEW, "dev1 output ln_width1=0x%x, ln_width2=0x%x\n", ln_width1, ln_width2); if (ln_width1 > ln_width2) { ln_width1 = ln_width2; } width |= pow2_to_link_width[ln_width1] << 4; - printk(BIOS_SPEW, "dev1 input|output width=0x%x\r\n", width); + printk(BIOS_SPEW, "dev1 input|output width=0x%x\n", width); /* See if I am changing dev1's width */ old_width = pci_read_config8(dev1, pos1 + LINK_WIDTH(offs1) + 1); old_width &= 0x77; needs_reset |= old_width != width; - printk(BIOS_SPEW, "old dev1 input|output width=0x%x\r\n", width); + printk(BIOS_SPEW, "old dev1 input|output width=0x%x\n", width); /* Set dev1's widths */ pci_write_config8(dev1, pos1 + LINK_WIDTH(offs1) + 1, width); /* Calculate dev2's width */ width = ((width & 0x70) >> 4) | ((width & 0x7) << 4); - printk(BIOS_SPEW, "dev2 input|output width=0x%x\r\n", width); + printk(BIOS_SPEW, "dev2 input|output width=0x%x\n", width); /* See if I am changing dev2's width */ old_width = pci_read_config8(dev2, pos2 + LINK_WIDTH(offs2) + 1); old_width &= 0x77; needs_reset |= old_width != width; - printk(BIOS_SPEW, "old dev2 input|output width=0x%x\r\n", width); + printk(BIOS_SPEW, "old dev2 input|output width=0x%x\n", width); /* Set dev2's widths */ pci_write_config8(dev2, pos2 + LINK_WIDTH(offs2) + 1, width); @@ -371,7 +371,7 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of print_err("udev="); print_err_hex32(udev); print_err("\tupos="); print_err_hex32(upos); print_err("\tuoffs="); print_err_hex32(uoffs); - print_err("\tHT link capability not found\r\n"); + print_err("\tHT link capability not found\n"); break; } @@ -852,16 +852,16 @@ static int optimize_link_incoherent_ht(struct sys_info *sysinfo) unsigned link_pair_num = sysinfo->link_pair_num; - printk(BIOS_SPEW, "entering optimize_link_incoherent_ht\r\n"); - printk(BIOS_SPEW, "sysinfo->link_pair_num=0x%x\r\n", link_pair_num); + printk(BIOS_SPEW, "entering optimize_link_incoherent_ht\n"); + printk(BIOS_SPEW, "sysinfo->link_pair_num=0x%x\n", link_pair_num); for(i=0; i< link_pair_num; i++) { struct link_pair_st *link_pair= &sysinfo->link_pair[i]; reset_needed |= ht_optimize_link(link_pair->udev, link_pair->upos, link_pair->uoffs, link_pair->dev, link_pair->pos, link_pair->offs); - printk(BIOS_SPEW, "after ht_optimize_link for link pair %d, reset_needed=0x%x\r\n", i, reset_needed); + printk(BIOS_SPEW, "after ht_optimize_link for link pair %d, reset_needed=0x%x\n", i, reset_needed); } reset_needed |= optimize_link_read_pointers_chain(sysinfo->ht_c_num); - printk(BIOS_SPEW, "after optimize_link_read_pointers_chain, reset_needed=0x%x\r\n", reset_needed); + printk(BIOS_SPEW, "after optimize_link_read_pointers_chain, reset_needed=0x%x\n", reset_needed); return reset_needed; diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 5500ce65a7..3d853378d8 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -1224,7 +1224,7 @@ static unsigned int cpu_bus_scan(device_t dev, unsigned int max) e0_later_single_core = 0; } if(e0_later_single_core) { - printk(BIOS_DEBUG, "\tFound Rev E or Rev F later single core\r\n"); + printk(BIOS_DEBUG, "\tFound Rev E or Rev F later single core\n"); j=1; } diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index 55cdcaf703..4e402e6d7a 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -25,7 +25,7 @@ static inline void print_debug_dqs(const char *str, unsigned val, unsigned level { #if DQS_TRAIN_DEBUG > 0 if(DQS_TRAIN_DEBUG > level) { - printk(BIOS_DEBUG, "%s%x\r\n", str, val); + printk(BIOS_DEBUG, "%s%x\n", str, val); } #endif } @@ -34,7 +34,7 @@ static inline void print_debug_dqs_pair(const char *str, unsigned val, const cha { #if DQS_TRAIN_DEBUG > 0 if(DQS_TRAIN_DEBUG > level) { - printk(BIOS_DEBUG, "%s%08x%s%08x\r\n", str, val, str2, val2); + printk(BIOS_DEBUG, "%s%08x%s%08x\n", str, val, str2, val2); } #endif } @@ -43,14 +43,14 @@ static inline void print_debug_dqs_tsc(const char *str, unsigned i, unsigned val { #if DQS_TRAIN_DEBUG > 0 if(DQS_TRAIN_DEBUG > level) { - printk(BIOS_DEBUG, "%s[%02x]=%08x%08x\r\n", str, i, val, val2); + printk(BIOS_DEBUG, "%s[%02x]=%08x%08x\n", str, i, val, val2); } #endif } static inline void print_debug_dqs_tsc_x(const char *str, unsigned i, unsigned val, unsigned val2) { - printk(BIOS_DEBUG, "%s[%02x]=%08x%08x\r\n", str, i, val, val2); + printk(BIOS_DEBUG, "%s[%02x]=%08x%08x\n", str, i, val, val2); } @@ -583,7 +583,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st } } - print_debug_dqs("\r\nTrainRcvEn: 0 ctrl", ctrl->node_id, 0); + print_debug_dqs("\nTrainRcvEn: 0 ctrl", ctrl->node_id, 0); print_debug_addr("TrainRcvEn: buf_a:", buf_a); @@ -1401,7 +1401,7 @@ static unsigned TrainDQSRdWrPos(const struct mem_controller *ctrl, struct sys_in } - print_debug_dqs("\r\nTrainDQSRdWrPos: 0 ctrl ", ctrl->node_id, 0); + print_debug_dqs("\nTrainDQSRdWrPos: 0 ctrl ", ctrl->node_id, 0); printk(BIOS_DEBUG, "TrainDQSRdWrPos: buf_a:%p\n", buf_a); @@ -1525,25 +1525,25 @@ static void SetEccDQSRdWrPos(const struct mem_controller *ctrl, struct sys_info static unsigned train_DqsRcvrEn(const struct mem_controller *ctrl, unsigned Pass, struct sys_info *sysinfo) { - print_debug_dqs("\r\ntrain_DqsRcvrEn: begin ctrl ", ctrl->node_id, 0); + print_debug_dqs("\ntrain_DqsRcvrEn: begin ctrl ", ctrl->node_id, 0); if(TrainRcvrEn(ctrl, Pass, sysinfo)) { return 1; } - print_debug_dqs("\r\ntrain_DqsRcvrEn: end ctrl ", ctrl->node_id, 0); + print_debug_dqs("\ntrain_DqsRcvrEn: end ctrl ", ctrl->node_id, 0); return 0; } static unsigned train_DqsPos(const struct mem_controller *ctrl, struct sys_info *sysinfo) { - print_debug_dqs("\r\ntrain_DqsPos: begin ctrl ", ctrl->node_id, 0); + print_debug_dqs("\ntrain_DqsPos: begin ctrl ", ctrl->node_id, 0); if(TrainDQSRdWrPos(ctrl, sysinfo) != 0) { - printk(BIOS_ERR, "\r\nDQS Training Rd Wr failed ctrl%02x\r\n", ctrl->node_id); + printk(BIOS_ERR, "\nDQS Training Rd Wr failed ctrl%02x\n", ctrl->node_id); return 1; } else { SetEccDQSRdWrPos(ctrl, sysinfo); } - print_debug_dqs("\r\ntrain_DqsPos: end ctrl ", ctrl->node_id, 0); + print_debug_dqs("\ntrain_DqsPos: end ctrl ", ctrl->node_id, 0); return 0; } @@ -1700,7 +1700,7 @@ static unsigned int range_to_mtrr(unsigned int reg, } sizek = 1 << align; #if CONFIG_MEM_TRAIN_SEQ != 1 - printk(BIOS_DEBUG, "Setting variable MTRR %d, base: %4ldMB, range: %4ldMB, type %s\r\n", + printk(BIOS_DEBUG, "Setting variable MTRR %d, base: %4ldMB, range: %4ldMB, type %s\n", reg, range_startk >>10, sizek >> 10, (type==MTRR_TYPE_UNCACHEABLE)?"UC": ((type==MTRR_TYPE_WRBACK)?"WB":"Other") @@ -1952,7 +1952,7 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc printk(BIOS_DEBUG, "DQS Training:RcvrEn:Pass1: %02x\n", i); if(train_DqsRcvrEn(ctrl+i, 1, sysinfo)) goto out; - printk(BIOS_DEBUG, " done\r\n"); + printk(BIOS_DEBUG, " done\n"); } tsc[1] = rdtsc(); @@ -1970,7 +1970,7 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc printk(BIOS_DEBUG, "DQS Training:DQSPos: %02x\n", i); if(train_DqsPos(ctrl+i, sysinfo)) goto out; - printk(BIOS_DEBUG, " done\r\n"); + printk(BIOS_DEBUG, " done\n"); } tsc[3] = rdtsc(); @@ -1983,7 +1983,7 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc printk(BIOS_DEBUG, "DQS Training:RcvrEn:Pass2: %02x\n", i); if(train_DqsRcvrEn(ctrl+i, 2, sysinfo)) goto out; - printk(BIOS_DEBUG, " done\r\n"); + printk(BIOS_DEBUG, " done\n"); sysinfo->mem_trained[i]=1; dqs_save_MC_NVRAM((ctrl+i)->f2); } @@ -2033,7 +2033,7 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info } if(v) { - printk(BIOS_DEBUG, " done\r\n"); + printk(BIOS_DEBUG, " done\n"); tsc[1] = rdtsc(); printk(BIOS_DEBUG, "set DQS timing:DQSPos: %02x\n", i); } @@ -2044,7 +2044,7 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info } if(v) { - printk(BIOS_DEBUG, " done\r\n"); + printk(BIOS_DEBUG, " done\n"); tsc[2] = rdtsc(); printk(BIOS_DEBUG, "set DQS timing:RcvrEn:Pass2: %02x\n", i); @@ -2055,7 +2055,7 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info } if(v) { - printk(BIOS_DEBUG, " done\r\n"); + printk(BIOS_DEBUG, " done\n"); tsc[3] = rdtsc(); } diff --git a/src/northbridge/amd/amdk8/raminit_test.c b/src/northbridge/amd/amdk8/raminit_test.c index 329c1afb83..5700c522a2 100644 --- a/src/northbridge/amd/amdk8/raminit_test.c +++ b/src/northbridge/amd/amdk8/raminit_test.c @@ -394,7 +394,7 @@ static void test1(void) #if 0 print_debug("spd_count: "); print_debug_hex32(spd_count); - print_debug("\r\n"); + print_debug("\n"); #endif } @@ -410,9 +410,9 @@ static void do_test2(int i) reset_tests(); spd_fail_count = i; - print_debug("\r\nSPD will fail after: "); + print_debug("\nSPD will fail after: "); print_debug_hex32(spd_fail_count); - print_debug(" accesses.\r\n"); + print_debug(" accesses.\n"); memcpy(&spd_data[0*256], spd_micron_512MB_DDR333, 256); memcpy(&spd_data[1*256], spd_micron_512MB_DDR333, 256); diff --git a/src/northbridge/amd/amdk8/setup_resource_map.c b/src/northbridge/amd/amdk8/setup_resource_map.c index cd7b3b54b4..ec3c0cf919 100644 --- a/src/northbridge/amd/amdk8/setup_resource_map.c +++ b/src/northbridge/amd/amdk8/setup_resource_map.c @@ -5,14 +5,14 @@ static void setup_resource_map_offset(const unsigned int *register_values, int m int i; // print_debug("setting up resource map offset...."); #if 0 - print_debug("\r\n"); + print_debug("\n"); #endif for(i = 0; i < max; i += 3) { device_t dev; unsigned where; unsigned long reg; #if 0 - prink_debug("%08x <- %08x\r\n", register_values[i] + offset_pci_dev, register_values[i+2]); + prink_debug("%08x <- %08x\n", register_values[i] + offset_pci_dev, register_values[i+2]); #endif dev = (register_values[i] & ~0xfff) + offset_pci_dev; where = register_values[i] & 0xfff; @@ -27,7 +27,7 @@ static void setup_resource_map_offset(const unsigned int *register_values, int m pci_write_config32(register_values[i], reg); #endif } -// print_debug("done.\r\n"); +// print_debug("done.\n"); } #define RES_PCI_IO 0x10 @@ -45,11 +45,11 @@ static void setup_resource_map_x_offset(const unsigned int *register_values, int #endif #if RES_DEBUG - print_debug("\r\n"); + print_debug("\n"); #endif for(i = 0; i < max; i += 4) { #if RES_DEBUG - printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\r\n", + printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\n", i>>2, register_values[i], register_values[i+1] + ( (register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0), register_values[i+2], @@ -112,7 +112,7 @@ static void setup_resource_map_x_offset(const unsigned int *register_values, int } #if RES_DEBUG - print_debug("done.\r\n"); + print_debug("done.\n"); #endif } static void setup_resource_map_x(const unsigned int *register_values, int max) @@ -125,11 +125,11 @@ static void setup_resource_map_x(const unsigned int *register_values, int max) #endif #if RES_DEBUG - print_debug("\r\n"); + print_debug("\n"); #endif for(i = 0; i < max; i += 4) { #if RES_DEBUG - printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\r\n", + printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\n", i/4, register_values[i],register_values[i+1], register_values[i+2], register_values[i+3]); #endif switch (register_values[i]) { @@ -188,7 +188,7 @@ static void setup_resource_map_x(const unsigned int *register_values, int max) } #if RES_DEBUG - print_debug("done.\r\n"); + print_debug("done.\n"); #endif } @@ -223,7 +223,7 @@ static void setup_iob_resource_map(const unsigned int *register_values, int max) print_debug(" -> "); reg = inb(where); print_debug_hex8(reg); - print_debug("\r\n"); + print_debug("\n"); #endif } } @@ -262,7 +262,7 @@ static void setup_io_resource_map(const unsigned int *register_values, int max) print_debug(" -> "); reg = inl(where); print_debug_hex32(reg); - print_debug("\r\n"); + print_debug("\n"); #endif } } @@ -289,7 +289,7 @@ static void setup_mem_resource_map(const unsigned int *register_values, int max) print_debug(" RB "); reg = read32(where); print_debug_hex32(reg); - print_debug("\r\n"); + print_debug("\n"); #endif } } diff --git a/src/northbridge/amd/gx1/raminit.c b/src/northbridge/amd/gx1/raminit.c index 02ff7fb599..f61a69b4f8 100644 --- a/src/northbridge/amd/gx1/raminit.c +++ b/src/northbridge/amd/gx1/raminit.c @@ -143,7 +143,7 @@ int comp_banks; #if 0 print_debug("MC_BANK_CFG = "); print_debug_hex32(getGX1Mem(GX_BASE + MC_BANK_CFG)); - print_debug("\r\n"); + print_debug("\n"); #endif /* retrieve the page size from the MC register */ @@ -152,7 +152,7 @@ int comp_banks; #if 0 print_debug(" page_size = "); print_debug_hex32(page_size); - print_debug("\r\n"); + print_debug("\n"); #endif comp_banks = (((getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_COMP_BNK << dimm_shift)) >> dimm_shift) >> 12); @@ -169,7 +169,7 @@ int comp_banks; #if 0 print_debug("MC_BANK_CFG = "); print_debug_hex32(getGX1Mem(GX_BASE + MC_BANK_CFG)); - print_debug("\r\n"); + print_debug("\n"); #endif return(getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_MOD_BNK << dimm_shift)); } @@ -181,7 +181,7 @@ int page_size = 0x800; /* Smallest page = 1K * 2 banks */ #if 0 print_debug("MC_BANK_CFG = "); print_debug_hex32(getGX1Mem(GX_BASE + MC_BANK_CFG)); - print_debug("\r\n"); + print_debug("\n"); #endif page_size = page_size << (((getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_PG_SZ << dimm_shift)) >> dimm_shift) >> 4); @@ -189,7 +189,7 @@ int page_size = 0x800; /* Smallest page = 1K * 2 banks */ #if 0 print_debug(" page_size = "); print_debug_hex32(page_size); - print_debug("\r\n"); + print_debug("\n"); #endif setGX1Mem(0, TEST_DATA1); @@ -203,7 +203,7 @@ int page_size = 0x800; /* Smallest page = 1K * 2 banks */ #if 0 print_debug("MC_BANK_CFG = "); print_debug_hex32(getGX1Mem(GX_BASE + MC_BANK_CFG)); - print_debug("\r\n"); + print_debug("\n"); #endif return(getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_COMP_BNK << dimm_shift)); } @@ -225,7 +225,7 @@ unsigned int probe_config; #if 0 print_debug(" Page size Config = "); print_debug_hex32(page_size_config << dimm_shift); - print_debug("\r\n"); + print_debug("\n"); #endif return(page_size_config << dimm_shift); } @@ -257,7 +257,7 @@ unsigned int test; print_debug("Probing for DIMM"); print_debug_char((dimm_shift >> 4) + 0x30); - print_debug("\r\n"); + print_debug("\n"); setGX1Mem(0, TEST_DATA1); setGX1Mem(0x100, 0); @@ -269,7 +269,7 @@ unsigned int test; print_debug(" Found DIMM"); print_debug_char((dimm_shift >> 4) + 0x30); - print_debug("\r\n"); + print_debug("\n"); return 1; } @@ -285,7 +285,7 @@ static int size_memory(int dimm_shift, unsigned int mem_config) print_debug(" Page Size: "); print_debug_hex32(0x400 << ((mem_config & (DIMM_PG_SZ << dimm_shift)) >> (dimm_shift + 4))); - print_debug("\r\n"); + print_debug("\n"); /* Now do component banks detection */ @@ -294,7 +294,7 @@ static int size_memory(int dimm_shift, unsigned int mem_config) print_debug(" Component Banks: "); print_debug_char((((mem_config & (DIMM_COMP_BNK << dimm_shift)) >> (dimm_shift + 12)) ? 4 : 2) + 0x30); - print_debug("\r\n"); + print_debug("\n"); /* Now do module banks */ @@ -303,7 +303,7 @@ static int size_memory(int dimm_shift, unsigned int mem_config) print_debug(" Module Banks: "); print_debug_char((((mem_config & (DIMM_MOD_BNK << dimm_shift)) >> (dimm_shift + 14)) ? 2 : 1) + 0x30); - print_debug("\r\n"); + print_debug("\n"); mem_config &= (~(DIMM_SZ << dimm_shift)); mem_config |= (size_dimm(dimm_shift)); @@ -311,7 +311,7 @@ static int size_memory(int dimm_shift, unsigned int mem_config) print_debug(" DIMM size: "); print_debug_hex32(1 << ((mem_config & (DIMM_SZ << dimm_shift)) >> (dimm_shift + 8)) + 22); - print_debug("\r\n"); + print_debug("\n"); return (mem_config); } @@ -320,7 +320,7 @@ static void sdram_init(void) { unsigned int mem_config = 0x00700070; - print_debug("Setting up default parameters for memory\r\n"); + print_debug("Setting up default parameters for memory\n"); outb(0x70, 0x80); setGX1Mem(GX_BASE + MC_MEM_CNTRL2, 0x000007d8); /* Disable all CLKS, Shift = 3 */ @@ -335,7 +335,7 @@ unsigned int mem_config = 0x00700070; enable_dimm(); - print_debug("Sizing memory\r\n"); + print_debug("Sizing memory\n"); setGX1Mem(GX_BASE + MC_BANK_CFG, 0x00705740); do_refresh(); @@ -346,7 +346,7 @@ unsigned int mem_config = 0x00700070; print_debug("MC_BANK_CFG = "); print_debug_hex32(mem_config); - print_debug("\r\n"); + print_debug("\n"); setGX1Mem(GX_BASE + MC_BANK_CFG, mem_config); enable_dimm(); diff --git a/src/northbridge/amd/gx2/pll_reset.c b/src/northbridge/amd/gx2/pll_reset.c index 5e6b68ace6..040d7b7a4e 100644 --- a/src/northbridge/amd/gx2/pll_reset.c +++ b/src/northbridge/amd/gx2/pll_reset.c @@ -276,11 +276,11 @@ static void pll_reset(void) msr.lo |= PLLMSRlo1; wrmsr(GLCP_SYS_RSTPLL, msr); - print_debug("Reset PLL\n\r"); + print_debug("Reset PLL\n"); msr.lo |= PLLMSRlo2; wrmsr(GLCP_SYS_RSTPLL,msr); - print_debug("should not be here\n\r"); + print_debug("should not be here\n"); #endif print_err("shit"); while (1) @@ -289,7 +289,7 @@ static void pll_reset(void) if (msr.lo & GLCP_SYS_RSTPLL_SWFLAGS_MASK) { /* PLL is already set and we are reboot from PLL reset */ - print_debug("reboot from BIOS reset\n\r"); + print_debug("reboot from BIOS reset\n"); return; } @@ -310,11 +310,11 @@ static void pll_reset(void) msr.lo |= ((0xde << 16) | (1 << 26) | (1 << 24)); wrmsr(0x4c000014, msr); - print_debug("Reset PLL\n\r"); + print_debug("Reset PLL\n"); msr.lo |= ((1<<14) |(1<<13) | (1<<0)); wrmsr(0x4c000014,msr); - print_debug("should not be here\n\r"); + print_debug("should not be here\n"); } #endif // #if USE_GOODRICH_VERSION diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c index e45d696e35..b1cb1af6b3 100644 --- a/src/northbridge/amd/gx2/raminit.c +++ b/src/northbridge/amd/gx2/raminit.c @@ -21,13 +21,13 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) msr = rdmsr(0x2000001a); msr.lo = 0x0101; wrmsr(0x2000001a, msr); - //print_debug("sdram_enable step 2\r\n"); + //print_debug("sdram_enable step 2\n"); /* 3. release CKE mask to enable CKE */ msr = rdmsr(0x2000001d); msr.lo &= ~(0x03 << 8); wrmsr(0x2000201d, msr); - //print_debug("sdram_enable step 3\r\n"); + //print_debug("sdram_enable step 3\n"); /* 4. set and clear REF_TST 16 times, more shouldn't hurt * why this is before EMRS and MRS ? */ @@ -38,7 +38,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) msr.lo &= ~(0x01 << 3); wrmsr(0x20000018, msr); } - //print_debug("sdram_enable step 4\r\n"); + //print_debug("sdram_enable step 4\n"); /* 5. set refresh interval */ msr = rdmsr(0x20000018); @@ -50,7 +50,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) msr.lo &= ~(0x03 << 6); msr.lo |= (0x00 << 6); wrmsr(0x20000018, msr); - //print_debug("sdram_enable step 5\r\n"); + //print_debug("sdram_enable step 5\n"); /* 6. enable DLL, load Extended Mode Register by set and clear PROG_DRAM */ msr = rdmsr(0x20000018); @@ -58,7 +58,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) wrmsr(0x20000018, msr); msr.lo &= ~((0x01 << 28) | 0x01); wrmsr(0x20000018, msr); - //print_debug("sdram_enable step 6\r\n"); + //print_debug("sdram_enable step 6\n"); /* 7. Reset DLL, Bit 27 is undocumented in GX datasheet, * it is documented in LX datasheet */ @@ -68,7 +68,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) wrmsr(0x20000018, msr); msr.lo &= ~((0x01 << 27) | 0x01); wrmsr(0x20000018, msr); - //print_debug("sdram_enable step 7\r\n"); + //print_debug("sdram_enable step 7\n"); /* 8. load Mode Register by set and clear PROG_DRAM */ msr = rdmsr(0x20000018); @@ -76,7 +76,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) wrmsr(0x20000018, msr); msr.lo &= ~0x01; wrmsr(0x20000018, msr); - //print_debug("sdram_enable step 8\r\n"); + //print_debug("sdram_enable step 8\n"); /* wait 200 SDCLKs */ for (i = 0; i < 200; i++) @@ -107,7 +107,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* make sure there is nothing stale in the cache */ __asm__("wbinvd\n"); - print_debug("RAM DLL lock\r\n"); + print_debug("RAM DLL lock\n"); /* The RAM dll needs a write to lock on so generate a few dummy writes */ volatile unsigned long *ptr; for (i=0;i<5;i++) { diff --git a/src/northbridge/amd/lx/pll_reset.c b/src/northbridge/amd/lx/pll_reset.c index 45a2c9338c..08c19b48e5 100644 --- a/src/northbridge/amd/lx/pll_reset.c +++ b/src/northbridge/amd/lx/pll_reset.c @@ -68,7 +68,7 @@ static void pll_reset(char manualconf) __asm__ __volatile__("hlt\n"); } - print_debug("Done pll_reset\r\n"); + print_debug("Done pll_reset\n"); return; } diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c index d22efa61c0..15b5be6ea4 100644 --- a/src/northbridge/amd/lx/raminit.c +++ b/src/northbridge/amd/lx/raminit.c @@ -32,12 +32,12 @@ static void banner(const char *s) /* This is so ugly. */ print_debug("==========================="); print_debug(s); - print_debug("======================================\r\n"); + print_debug("======================================\n"); } void hcf(void) { - print_emerg("DIE\r\n"); + print_emerg("DIE\n"); /* this guarantees we flush the UART fifos (if any) and also * ensures that things, in general, keep going so no debug output * is lost @@ -200,7 +200,7 @@ static void checkDDRMax(void) /* current speed > max speed? */ if (GeodeLinkSpeed() > speed) { - print_emerg("DIMM overclocked. Check GeodeLink Speed\r\n"); + print_emerg("DIMM overclocked. Check GeodeLink Speed\n"); POST_CODE(POST_PLL_MEM_FAIL); hcf(); } @@ -340,7 +340,7 @@ static void setCAS(void) } else if ((casmap0 &= casmap1)) { spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap0)]; } else { - print_emerg("DIMM CAS Latencies not compatible\r\n"); + print_emerg("DIMM CAS Latencies not compatible\n"); POST_CODE(ERROR_DIFF_DIMMS); hcf(); } @@ -532,7 +532,7 @@ static void EnableMTest(void) msr.lo |= CFCLK_LOWER_TRISTATE_DIS_SET; wrmsr(MC_CFCLK_DBUG, msr); - print_info("Enabled MTest for TLA debug\r\n"); + print_info("Enabled MTest for TLA debug\n"); } static void sdram_set_registers(const struct mem_controller *ctrl) @@ -576,7 +576,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) banner("Check DIMM 0"); /* Check DIMM is not Register and not Buffered DIMMs. */ if ((spd_byte != 0xFF) && (spd_byte & 3)) { - print_emerg("DIMM0 NOT COMPATIBLE\r\n"); + print_emerg("DIMM0 NOT COMPATIBLE\n"); POST_CODE(ERROR_UNSUPPORTED_DIMM); hcf(); } @@ -649,7 +649,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) msr = rdmsr(MC_CF07_DATA); if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) == ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) { - print_emerg("No memory in the system\r\n"); + print_emerg("No memory in the system\n"); POST_CODE(ERROR_NO_DIMMS); hcf(); } -- cgit v1.2.3