From 49bb26a469c4e0dc4fd2414c11c9926046199730 Mon Sep 17 00:00:00 2001 From: zbao Date: Fri, 3 Aug 2012 15:44:42 +0800 Subject: AMD NB: Limit the device field to 5 bits. (Propagation) Apply the change http://review.coreboot.org/1264 to all the AMD northbridge. Change-Id: Ied74d6f579d2c0350288e2619d7810f8d44fa574 Signed-off-by: Zheng Bao Signed-off-by: zbao Reviewed-on: http://review.coreboot.org/1403 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/northbridge/amd/agesa/family10/northbridge.c | 4 ++-- src/northbridge/amd/agesa/family12/northbridge.c | 6 +++++- src/northbridge/amd/agesa/family14/northbridge.c | 6 +++++- src/northbridge/amd/agesa/family15/northbridge.c | 4 ++-- src/northbridge/amd/amdfam10/northbridge.c | 4 ++-- 5 files changed, 16 insertions(+), 8 deletions(-) (limited to 'src/northbridge/amd') diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 831aec095c..8cc9475c45 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -361,8 +361,8 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi static device_t get_node_pci(u32 nodeid, u32 fn) { -#if NODE_NUMS == 64 - if (nodeid < 32) { +#if NODE_NUMS + CONFIG_CDB >= 32 + if ((CONFIG_CDB + nodeid) < 32) { return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); } else { return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn)); diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index f3f03a42b6..af1d4f064c 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -50,7 +50,11 @@ static unsigned fx_devs=0; device_t get_node_pci(u32 nodeid, u32 fn) { - return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); + if ((CONFIG_CDB + nodeid) < 32) { + return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); + } else { + return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn)); + } } diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index af6dfcc297..a03939cde4 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -51,7 +51,11 @@ static unsigned fx_devs = 0; device_t get_node_pci(u32 nodeid, u32 fn) { - return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); + if ((CONFIG_CDB + nodeid) < 32) { + return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); + } else { + return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn)); + } } static void get_fx_devs(void) diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index a080293503..8d64a3068b 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -122,8 +122,8 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi static device_t get_node_pci(u32 nodeid, u32 fn) { -#if MAX_NODE_NUMS == 64 - if (nodeid < 32) { +#if MAX_NODE_NUMS + CONFIG_CDB >= 32 + if ((CONFIG_CDB + nodeid) < 32) { return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); } else { return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn)); diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 15b29f6574..aa15fdd6e5 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -63,8 +63,8 @@ static unsigned fx_devs=0; device_t get_node_pci(u32 nodeid, u32 fn) { -#if NODE_NUMS == 64 - if(nodeid<32) { +#if NODE_NUMS + CONFIG_CDB >= 32 + if((CONFIG_CDB + nodeid) < 32) { return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); } else { return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn)); -- cgit v1.2.3