From 15279a9696c70b82c2223264a505da9122f9aa7b Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 28 Jul 2016 21:05:26 +0200 Subject: src/northbridge: Capitalize CPU, RAM and ROM Change-Id: I5aa27f06f82a8309afb6e06c9e462e5792aa9986 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/15940 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/northbridge/amd/amdfam10/early_ht.c | 2 +- src/northbridge/amd/amdht/h3finit.c | 6 +++--- src/northbridge/amd/amdk8/coherent_ht.c | 6 +++--- src/northbridge/amd/amdk8/early_ht.c | 2 +- src/northbridge/amd/amdk8/f.h | 2 +- src/northbridge/amd/amdk8/incoherent_ht.c | 4 ++-- src/northbridge/amd/amdk8/raminit.c | 6 +++--- src/northbridge/amd/amdk8/raminit_f.c | 4 ++-- src/northbridge/amd/gx2/northbridgeinit.c | 2 +- src/northbridge/amd/lx/northbridge.c | 4 ++-- src/northbridge/amd/lx/northbridgeinit.c | 2 +- 11 files changed, 20 insertions(+), 20 deletions(-) (limited to 'src/northbridge/amd') diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c index 1199a50430..3e59a324e7 100644 --- a/src/northbridge/amd/amdfam10/early_ht.c +++ b/src/northbridge/amd/amdfam10/early_ht.c @@ -41,7 +41,7 @@ static void enumerate_ht_chain(void) if so, don't need to go through the chain */ /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it. - * On most boards this just happens. If a cpu has multiple + * On most boards this just happens. If a CPU has multiple * non Coherent links the appropriate bus registers for the * links needs to be programed to point at bus 0. */ diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index 6a45f10306..bfda13d9e7 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -917,7 +917,7 @@ static void lookupComputeAndLoadRoutingTables(sMainData *pDat) * * Description: * Find the total number of cores and update the number of nodes and cores in all cpus. - * Limit cpu config access to installed cpus. + * Limit CPU config access to installed cpus. * * Parameters: * @param[in] sMainData* pDat = our global state, number of nodes discovered. @@ -1357,12 +1357,12 @@ static void regangLinks(sMainData *pDat) pDat->PortList[i+1].SelRegang = FALSE; if ( (pDat->PortList[i].Type != PORTLIST_TYPE_CPU) || (pDat->PortList[i+1].Type != PORTLIST_TYPE_CPU)) - continue; /* Only process cpu to cpu links */ + continue; /* Only process CPU to CPU links */ for (j = i+2; j < pDat->TotalLinks*2; j += 2) { if ( (pDat->PortList[j].Type != PORTLIST_TYPE_CPU) || (pDat->PortList[j+1].Type != PORTLIST_TYPE_CPU) ) - continue; /* Only process cpu to cpu links */ + continue; /* Only process CPU to CPU links */ if (pDat->PortList[i].NodeID != pDat->PortList[j].NodeID) continue; /* Links must be from the same source */ diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index 8779ec7c7b..a7c3fc27c6 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -113,7 +113,7 @@ static inline void print_linkn (const char *strval, uint8_t byteval) static void disable_probes(void) { /* disable read/write/fill probes for uniprocessor setup - * they don't make sense if only one cpu is available + * they don't make sense if only one CPU is available */ /* Hypetransport Transaction Control Register @@ -1597,7 +1597,7 @@ static void coherent_ht_finalize(unsigned nodes) } #endif - /* set up cpu count and node count and enable Limit + /* set up CPU count and node count and enable Limit * Config Space Range for all available CPUs. * Also clear non coherent hypertransport bus range * registers on Hammer A0 revision. @@ -1622,7 +1622,7 @@ static void coherent_ht_finalize(unsigned nodes) #endif pci_write_config32(dev, 0x60, val); - /* Only respond to real cpu pci configuration cycles + /* Only respond to real CPU pci configuration cycles * and optimize the HT settings */ val=pci_read_config32(dev, HT_TRANSACTION_CONTROL); diff --git a/src/northbridge/amd/amdk8/early_ht.c b/src/northbridge/amd/amdk8/early_ht.c index 6449f4b1f5..1bc34e42f1 100644 --- a/src/northbridge/amd/amdk8/early_ht.c +++ b/src/northbridge/amd/amdk8/early_ht.c @@ -8,7 +8,7 @@ static void enumerate_ht_chain(void) /* CONFIG_HT_CHAIN_UNITID_BASE could be 0 (only one ht device in the ht chain), if so, don't need to go through the chain */ /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it. - * On most boards this just happens. If a cpu has multiple + * On most boards this just happens. If a CPU has multiple * non Coherent links the appropriate bus registers for the * links needs to be programed to point at bus 0. */ diff --git a/src/northbridge/amd/amdk8/f.h b/src/northbridge/amd/amdk8/f.h index af4658dd8e..f83282bfeb 100644 --- a/src/northbridge/amd/amdk8/f.h +++ b/src/northbridge/amd/amdk8/f.h @@ -535,7 +535,7 @@ static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo) unsigned needs_reset = 0; - if(sysinfo->nodes == 1) return; // in case only one cpu installed + if(sysinfo->nodes == 1) return; // in case only one CPU installed for(i=1; inodes; i++) { /* Skip everything if I don't have any memory on this controller */ diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c index d765fc7003..12b8290dd1 100644 --- a/src/northbridge/amd/amdk8/incoherent_ht.c +++ b/src/northbridge/amd/amdk8/incoherent_ht.c @@ -481,7 +481,7 @@ static int ht_setup_chain(device_t udev, unsigned upos) #endif /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it. - * On most boards this just happens. If a cpu has multiple + * On most boards this just happens. If a CPU has multiple * non Coherent links the appropriate bus registers for the * links needs to be programed to point at bus 0. */ @@ -631,7 +631,7 @@ static int ht_setup_chains(uint8_t ht_c_num) #endif { /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it. - * On most boards this just happens. If a cpu has multiple + * On most boards this just happens. If a CPU has multiple * non Coherent links the appropriate bus registers for the * links needs to be programed to point at bus 0. */ diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index fbcb8879f8..f502287d22 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -859,7 +859,7 @@ static void set_top_mem(unsigned tom_k, unsigned hole_startk) } /* Leave a 64M hole between TOP_MEM and TOP_MEM2 - * so I can see my rom chip and other I/O devices. + * so I can see my ROM chip and other I/O devices. */ if (tom_k >= 0x003f0000) { #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -1243,7 +1243,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, long dimm_ma ((dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) { goto single_channel; } - /* If the cpu is not capable of doing dual channels don't do dual channels */ + /* If the CPU is not capable of doing dual channels don't do dual channels */ nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); if (!(nbcap & NBCAP_128Bit)) { goto single_channel; @@ -2476,7 +2476,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) //FIXME add enable node interleaving here -- yhlu /*needed? - 1. check how many nodes we have , if not all has ram installed get out + 1. check how many nodes we have , if not all has RAM installed get out 2. check cs_base lo is 0, node 0 f2 0x40,,,,, if any one is not using lo is CS_BASE, get out 3. check if other node is the same as node 0 about f2 0x40,,,,, otherwise get out 4. if all ready enable node_interleaving in f1 0x40..... of every node diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index cd4b9fbf52..8ed0335703 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -1054,7 +1054,7 @@ static void set_top_mem(unsigned tom_k, unsigned hole_startk) } /* Leave a 64M hole between TOP_MEM and TOP_MEM2 - * so I can see my rom chip and other I/O devices. + * so I can see my ROM chip and other I/O devices. */ if (tom_k >= 0x003f0000) { #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -1460,7 +1460,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i ((meminfo->dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) { goto single_channel; } - /* If the cpu is not capable of doing dual channels don't do dual channels */ + /* If the CPU is not capable of doing dual channels don't do dual channels */ nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); if (!(nbcap & NBCAP_128Bit)) { goto single_channel; diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c index efbe51ef11..f21d717a55 100644 --- a/src/northbridge/amd/gx2/northbridgeinit.c +++ b/src/northbridge/amd/gx2/northbridgeinit.c @@ -538,7 +538,7 @@ static void rom_shadow_settings(void) * * DEVRC_RCONF_DEFAULT: * ROMRC(63:56) = 04h ; write protect ROMBASE - * ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of rom chipselect area + * ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of ROM chipselect area * DEVRC(35:28) = 39h ; cache disabled in PCI memory + WS bit on + Write Combine + write burst. * SYSTOP(27:8) = top of system memory * SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index 0ff7917c7d..2ba4a0415d 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -46,7 +46,7 @@ #define WRITE_COMBINE (1<<4) #define WRITE_SERIALIZE (1<<5) -/* ram has none of this stuff */ +/* RAM has none of this stuff */ #define RAM_PROPERTIES (0) #define DEVICE_PROPERTIES (WRITE_SERIALIZE|CACHE_DISABLE) #define ROM_PROPERTIES (WRITE_SERIALIZE|WRITE_PROTECT|CACHE_DISABLE) @@ -86,7 +86,7 @@ struct msr_defaults { /* for 180a, for now, we assume VSM will configure it */ /* 180b is left at reset value,a0000-bffff is non-cacheable */ /* 180c, c0000-dffff is set to write serialize and non-cachable */ - /* oops, 180c will be set by cpu bug handling in cpubug.c */ + /* oops, 180c will be set by CPU bug handling in cpubug.c */ //{0x180c, {.hi = MSR_WS_CD_DEFAULT, .lo = MSR_WS_CD_DEFAULT}}, /* 180d is left at default, e0000-fffff is non-cached */ /* we will assume 180e, the ssm region configuration, is left at default or set by VSM */ diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c index 08259f8cc9..6c48fb4155 100644 --- a/src/northbridge/amd/lx/northbridgeinit.c +++ b/src/northbridge/amd/lx/northbridgeinit.c @@ -591,7 +591,7 @@ static void rom_shadow_settings(void) * * DEVRC_RCONF_DEFAULT: * ROMRC(63:56) = 04h ; write protect ROMBASE - * ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of rom chipselect area + * ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of ROM chipselect area * DEVRC(35:28) = 39h ; cache disabled in PCI memory + WS bit on + Write Combine + write burst. * SYSTOP(27:8) = top of system memory * SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough -- cgit v1.2.3