From 10d6fceaa05112cd8780a46fd1b1db565c4dd21c Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Mon, 7 Mar 2016 13:29:24 -0600 Subject: nb/amd/mct_ddr3: Train correct receiver in TrainDQSRdWrPos_D_Fam15 Change-Id: Ia26950a8297f0a7125c21e995c89a3fc68d9d8a9 Signed-off-by: Timothy Pearson Reviewed-on: https://review.coreboot.org/13932 Tested-by: Raptor Engineering Automated Test Stand Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'src/northbridge/amd') diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 3ab8e46098..fc081549f3 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -1342,14 +1342,11 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, Errors = 0; dual_rank = 0; - Receiver = mct_InitReceiver_D(pDCTstat, dct); - if (receiver_start > Receiver) - Receiver = receiver_start; /* There are four receiver pairs, loosely associated with chipselects. * This is essentially looping over each rank within each DIMM. */ - for (; Receiver < receiver_end; Receiver++) { + for (Receiver = receiver_start; Receiver < receiver_end; Receiver++) { dimm = (Receiver >> 1); if ((Receiver & 0x1) == 0) { /* Even rank of DIMM */ -- cgit v1.2.3