From 727ac0d26395e4522e56ee988f1ef0097d982d51 Mon Sep 17 00:00:00 2001 From: Michał Żygowski Date: Thu, 19 Dec 2019 12:56:21 +0100 Subject: AMD {SoC, AGESA, binaryPI}: Don't use both of _ADR and _HID MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PCI devices starting from 18 are processor configuration devices for each node and are not a bus itself. According to ACPI specification 6.3 section 6.1.5: "... _HID object must be used to describe any device that will be enumerated by OSPM. OSPM only enumerates a device when no bus enumerator can detect the device ID. ... Use the _ADR object to describe devices enumerated by bus enumerators other than OSPM." PCI device 18 with its functions has a standard enumerator, which is PCI enumerator so it needs a _ADR. Create a separate ACPI device for the processor configuration space. This fixes the ACPI compliance problem from CB:36318. Signed-off-by: Michał Żygowski Change-Id: Ie7b45ce8d9e4fdd80d90752bf51bba4d30041507 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37835 Reviewed-by: Patrick Georgi Reviewed-by: Paul Menzel Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/northbridge/amd/pi/00630F01/acpi/northbridge.asl | 5 ++++- src/northbridge/amd/pi/00660F01/acpi/northbridge.asl | 5 ++++- src/northbridge/amd/pi/00730F01/acpi/northbridge.asl | 5 ++++- 3 files changed, 12 insertions(+), 3 deletions(-) (limited to 'src/northbridge/amd/pi') diff --git a/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl index c2b3aac4c5..f3d42fa4ad 100644 --- a/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl @@ -17,7 +17,6 @@ External (TOM1) External (TOM2) Name(_HID, EISAID("PNP0A03")) /* PCI Express Root Bridge */ -Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Describe the Northbridge devices */ @@ -45,6 +44,10 @@ Device(AMRT) { Name(_ADR, 0x00000000) } /* end AMRT */ +Device(PCSD) { /* Processor configuration space devices */ + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ +} + /* Dev2 is also an external GFX bridge */ Device(PBR2) { Name(_ADR, 0x00020000) diff --git a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl index d54f985e90..761ff44399 100644 --- a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl @@ -18,7 +18,6 @@ External (TOM1) External (TOM2) Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ -Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Describe the Northbridge devices */ @@ -45,6 +44,10 @@ Device(AMRT) { Name(_ADR, 0x00000000) } /* end AMRT */ +Device(PCSD) { /* Processor configuration space devices */ + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ +} + /* Gpp 0 */ Device(PBR4) { Name(_ADR, 0x00020001) diff --git a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl index f74b31a080..3300db0c9c 100644 --- a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl @@ -18,7 +18,6 @@ External (TOM1) External (TOM2) Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ -Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Describe the Northbridge devices */ @@ -45,6 +44,10 @@ Device(AMRT) { Name(_ADR, 0x00000000) } /* end AMRT */ +Device(PCSD) { /* Processor configuration space devices */ + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ +} + /* Gpp 0 */ Device(PBR4) { Name(_ADR, 0x00020001) -- cgit v1.2.3