From 33ff44c37ccb96c209b002e5430deefc00cc5591 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 22 May 2018 01:15:22 +0300 Subject: binaryPI: Use pcidev_on_root() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We have constant CONFIG_CBB==0, replace ill dev_find_slot() with safe pcidev_on_root(); Change-Id: If536adf11aacef8faa3455692285552f97531df9 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/26483 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/northbridge/amd/pi/00730F01/dimmSpd.c | 2 +- src/northbridge/amd/pi/00730F01/northbridge.c | 18 +++++++++--------- 2 files changed, 10 insertions(+), 10 deletions(-) (limited to 'src/northbridge/amd/pi/00730F01') diff --git a/src/northbridge/amd/pi/00730F01/dimmSpd.c b/src/northbridge/amd/pi/00730F01/dimmSpd.c index c325418c24..79e046e3e4 100644 --- a/src/northbridge/amd/pi/00730F01/dimmSpd.c +++ b/src/northbridge/amd/pi/00730F01/dimmSpd.c @@ -27,7 +27,7 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINTN unused2, AGESA_READ_SPD_PARAMS *info) { int spdAddress; - DEVTREE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2)); + DEVTREE_CONST struct device *dev = pcidev_on_root(0x18, 2); DEVTREE_CONST struct northbridge_amd_pi_00730F01_config *config = dev->chip_info; if ((dev == 0) || (config == 0)) diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 4d9fc280b2..8030a3f7c7 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -104,7 +104,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi static struct device *get_node_pci(u32 nodeid, u32 fn) { - return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); + return pcidev_on_root(CONFIG_CDB + nodeid, fn); } static void get_fx_devs(void) @@ -581,7 +581,7 @@ static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current) uint8_t *p; acpi_ivrs_t *ivrs_agesa; - struct device *nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device *nb_dev = pcidev_on_root(0x0, 0); if (!nb_dev) { printk(BIOS_WARNING, "%s: G-series northbridge device not present!\n", __func__); @@ -786,12 +786,12 @@ static void fam16_finalize(void *chip_info) { struct device *dev; u32 value; - dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */ + dev = pcidev_on_root(0, 0); /* clear IoapicSbFeatureEn */ pci_write_config32(dev, 0xF8, 0); pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ /* disable No Snoop */ - dev = dev_find_slot(0, PCI_DEVFN(1, 1)); + dev = pcidev_on_root(1, 1); value = pci_read_config32(dev, 0x60); value &= ~(1 << 11); pci_write_config32(dev, 0x60, value); @@ -1090,7 +1090,7 @@ static void cpu_bus_scan(struct device *dev) printk(BIOS_SPEW, "MullinsPI Debug: AMD Topology Number of Modules (@0x%p) is %d\n", modules_ptr, modules); printk(BIOS_SPEW, "MullinsPI Debug: AMD Topology Number of IOAPICs (@0x%p) is %d\n", options, (int)options->CfgPlatNumIoApics); - dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); + dev_mc = pcidev_on_root(CONFIG_CDB, 0); if (!dev_mc) { printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB); die(""); @@ -1119,7 +1119,7 @@ static void cpu_bus_scan(struct device *dev) pbus = dev_mc->bus; /* Find the cpu's pci device */ - cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(devn, 0)); + cdb_dev = pcidev_on_root(devn, 0); if (!cdb_dev) { /* If I am probing things in a weird order * ensure all of the cpu's pci devices are found. @@ -1129,7 +1129,7 @@ static void cpu_bus_scan(struct device *dev) cdb_dev = pci_probe_dev(NULL, pbus, PCI_DEVFN(devn, fn)); } - cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(devn, 0)); + cdb_dev = pcidev_on_root(devn, 0); } else { /* Ok, We need to set the links for that device. * otherwise the device under it will not be scanned @@ -1142,11 +1142,11 @@ static void cpu_bus_scan(struct device *dev) family = (family >> 20) & 0xFF; if (family == 1) { //f10 u32 dword; - cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(devn, 3)); + cdb_dev = pcidev_on_root(devn, 3); dword = pci_read_config32(cdb_dev, 0xe8); siblings = ((dword & BIT15) >> 13) | ((dword & (BIT13 | BIT12)) >> 12); } else if (family == 7) {//f16 - cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(devn, 5)); + cdb_dev = pcidev_on_root(devn, 5); if (cdb_dev && cdb_dev->enabled) { siblings = pci_read_config32(cdb_dev, 0x84); siblings &= 0xFF; -- cgit v1.2.3