From a813160fbc37c41451afa01667669cf81b5799e7 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 19 Sep 2016 10:27:57 -0600 Subject: northbridge/amd: Improve code formatting Change-Id: I80a2753f22d5211c8be4e17e2338402286a2cadc Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/16645 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- .../amd/pi/00660F01/acpi/northbridge.asl | 16 +++++++-------- src/northbridge/amd/pi/00660F01/northbridge.c | 23 +++++++++++----------- 2 files changed, 19 insertions(+), 20 deletions(-) (limited to 'src/northbridge/amd/pi/00660F01') diff --git a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl index cde5182123..022b347d29 100644 --- a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl @@ -50,7 +50,7 @@ Device(PBR4) { Name(_ADR, 0x00020001) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ + If(PMOD) { Return(APS4) } /* APIC mode */ Return (PS4) /* PIC Mode */ } /* end _PRT */ } /* end PBR4 */ @@ -60,7 +60,7 @@ Device(PBR5) { Name(_ADR, 0x00020002) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ + If(PMOD) { Return(APS5) } /* APIC mode */ Return (PS5) /* PIC Mode */ } /* end _PRT */ } /* end PBR5 */ @@ -70,7 +70,7 @@ Device(PBR6) { Name(_ADR, 0x00020003) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ + If(PMOD) { Return(APS6) } /* APIC mode */ Return (PS6) /* PIC Mode */ } /* end _PRT */ } /* end PBR6 */ @@ -80,7 +80,7 @@ Device(PBR7) { Name(_ADR, 0x00020004) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ + If(PMOD) { Return(APS7) } /* APIC mode */ Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */ @@ -90,7 +90,7 @@ Device(PBR8) { Name(_ADR, 0x00020005) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS8) } /* APIC mode */ + If(PMOD) { Return(APS8) } /* APIC mode */ Return (PS8) /* PIC Mode */ } /* end _PRT */ } /* end PBR8 */ @@ -105,7 +105,7 @@ Device(PBRA) { Name(_ADR, 0x00030003) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APSA) } /* APIC mode */ + If(PMOD) { Return(APSA) } /* APIC mode */ Return (PSA) /* PIC Mode */ } /* end _PRT */ } /* end PBR8 */ @@ -115,7 +115,7 @@ Device(PBRB) { Name(_ADR, 0x00030004) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APSB) } /* APIC mode */ + If(PMOD) { Return(APSB) } /* APIC mode */ Return (PSB) /* PIC Mode */ } /* end _PRT */ } /* end PBR8 */ @@ -125,7 +125,7 @@ Device(PBRC) { Name(_ADR, 0x00030005) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APSC) } /* APIC mode */ + If(PMOD) { Return(APSC) } /* APIC mode */ Return (PSC) /* PIC Mode */ } /* end _PRT */ } /* end PBR8 */ diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index efee0a4f05..1ca0df98e4 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -100,10 +100,10 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit - for (i=0; ibus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ - if ((vga_pri->bus->secondary >= link->secondary ) && - (vga_pri->bus->secondary <= link->subordinate ) - ) + if ((vga_pri->bus->secondary >= link->secondary) && + (vga_pri->bus->secondary <= link->subordinate)) #endif break; } @@ -817,11 +816,11 @@ static void domain_set_resources(device_t dev) } /* split the region to accommodate pci memory space */ - if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) { + if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { if (basek <= mmio_basek) { unsigned pre_sizek; pre_sizek = mmio_basek - basek; - if (pre_sizek>0) { + if (pre_sizek > 0) { ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; @@ -1059,10 +1058,10 @@ static void cpu_bus_scan(device_t dev) siblings = 0; } int enable_node = cdb_dev && cdb_dev->enabled; - printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", + printk(BIOS_SPEW, "%s family%xh, core_max = 0x%x, core_nums = 0x%x, siblings = 0x%x\n", dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); - for (j = 0; j <= siblings; j++ ) { + for (j = 0; j <= siblings; j++) { u32 lapicid_start = 0; /* @@ -1081,10 +1080,10 @@ static void cpu_bus_scan(device_t dev) if ((node_nums * core_max) + ioapic_count >= 0x10) { lapicid_start = (ioapic_count - 1) / core_max; lapicid_start = (lapicid_start + 1) * core_max; - printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start); + printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start); } u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); - printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", + printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n", i, j, apic_id); device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); -- cgit v1.2.3