From c02b4fc9db3c3c1e263027382697b566127f66bb Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Mon, 22 Mar 2010 11:42:32 +0000 Subject: printk_foo -> printk(BIOS_FOO, ...) Signed-off-by: Stefan Reinauer Acked-by: Ronald G. Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/northbridge/amd/gx2/chipsetinit.c | 16 +++++------ src/northbridge/amd/gx2/northbridge.c | 40 +++++++++++++-------------- src/northbridge/amd/gx2/northbridgeinit.c | 46 +++++++++++++++---------------- 3 files changed, 51 insertions(+), 51 deletions(-) (limited to 'src/northbridge/amd/gx2') diff --git a/src/northbridge/amd/gx2/chipsetinit.c b/src/northbridge/amd/gx2/chipsetinit.c index 53a90535a5..cbb4e65620 100644 --- a/src/northbridge/amd/gx2/chipsetinit.c +++ b/src/northbridge/amd/gx2/chipsetinit.c @@ -87,7 +87,7 @@ static int is_5536(void){ msr_t msr; msr = rdmsr(GLIU_SB_GLD_MSR_CAP); msr.lo >>= 20; - printk_debug("is_5536: msr.lo is 0x%x(==5 means 5536)\n", msr.lo&0xf); + printk(BIOS_DEBUG, "is_5536: msr.lo is 0x%x(==5 means 5536)\n", msr.lo&0xf); return ((msr.lo&0xf) == 5); } /* ***************************************************************************/ @@ -205,10 +205,10 @@ static void ChipsetFlashSetup(void) int i; int numEnabled = 0; - printk_debug("ChipsetFlashSetup++\n"); + printk(BIOS_DEBUG, "ChipsetFlashSetup++\n"); for (i = 0; i < FlashInitTableLen; i++) { if (FlashInitTable[i].fType != FLASH_TYPE_NONE) { - printk_debug("Enable CS%d\n", i); + printk(BIOS_DEBUG, "Enable CS%d\n", i); /* we need to configure the memory/IO mask */ msr = rdmsr(FlashPort[i]); msr.hi = 0; /* start with the "enabled" bit clear */ @@ -221,13 +221,13 @@ static void ChipsetFlashSetup(void) else msr.hi &= ~0x00000004; msr.hi |= FlashInitTable[i].fMask; - printk_debug("WRMSR(0x%08X, %08X_%08X)\n", FlashPort[i], msr.hi, msr.lo); + printk(BIOS_DEBUG, "WRMSR(0x%08X, %08X_%08X)\n", FlashPort[i], msr.hi, msr.lo); wrmsr(FlashPort[i], msr); /* now write-enable the device */ msr = rdmsr(MDD_NORF_CNTRL); msr.lo |= (1 << i); - printk_debug("WRMSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL, msr.hi, msr.lo); + printk(BIOS_DEBUG, "WRMSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL, msr.hi, msr.lo); wrmsr(MDD_NORF_CNTRL, msr); /* update the number enabled */ @@ -239,10 +239,10 @@ static void ChipsetFlashSetup(void) if (0 != numEnabled) { msr = rdmsr(MDD_PIN_OPT); msr.lo &= ~1; /* PIN_OPT_IDE */ - printk_debug("WRMSR(0x%08X, %08X_%08X)\n", MDD_PIN_OPT, msr.hi, msr.lo); + printk(BIOS_DEBUG, "WRMSR(0x%08X, %08X_%08X)\n", MDD_PIN_OPT, msr.hi, msr.lo); wrmsr(MDD_PIN_OPT, msr); } - printk_debug("ChipsetFlashSetup--\n"); + printk(BIOS_DEBUG, "ChipsetFlashSetup--\n"); } @@ -359,7 +359,7 @@ chipsetinit (struct northbridge_amd_gx2_config *nb){ /* Flash Setup*/ - printk_err("%sDOING ChipsetFlashSetup()!!!!!!!!!!!!!!!!!!\n", nb->setupflash? " " : "NOT"); + printk(BIOS_ERR, "%sDOING ChipsetFlashSetup()!!!!!!!!!!!!!!!!!!\n", nb->setupflash? " " : "NOT"); if (nb->setupflash) ChipsetFlashSetup(); diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c index b20d3d7829..274277d7fc 100644 --- a/src/northbridge/amd/gx2/northbridge.c +++ b/src/northbridge/amd/gx2/northbridge.c @@ -32,7 +32,7 @@ sizeram(void) unsigned short dimm; msr = rdmsr(0x20000018); - printk_debug("sizeram: %08x:%08x\n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "sizeram: %08x:%08x\n", msr.hi, msr.lo); /* dimm 0 */ dimm = msr.hi; @@ -47,7 +47,7 @@ sizeram(void) if ((dimm & 7) != 7) sizem += (1 << ((dimm >> 12)-1)) * 8; - printk_debug("sizeram: sizem 0x%x\n", sizem); + printk(BIOS_DEBUG, "sizeram: sizem 0x%x\n", sizem); return sizem; } @@ -127,7 +127,7 @@ static void irq_init_steering(struct device *dev, uint16_t irq_map) { /* Set up IRQ steering */ uint32_t pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C; - printk_debug("%s(%08X [%08X], %04X)\n", __func__, dev, pciAddr, irq_map); + printk(BIOS_DEBUG, "%s(%08X [%08X], %04X)\n", __func__, dev, pciAddr, irq_map); /* The IRQ steering values (in hex) are effectively dcba, where: * represents the IRQ for INTA, @@ -160,7 +160,7 @@ setup_gx2_cache(void) int sizekbytes, sizereg; sizekbytes = sizeram() * 1024; - printk_debug("setup_gx2_cache: enable for %d KB\n", sizekbytes); + printk(BIOS_DEBUG, "setup_gx2_cache: enable for %d KB\n", sizekbytes); /* build up the rconf word. */ /* the SYSTOP bits 27:8 are actually the top bits from 31:12. Book fails to say that */ /* set romrp */ @@ -181,7 +181,7 @@ setup_gx2_cache(void) val |= RAM_PROPERTIES; msr.lo = val; msr.hi = (val >> 32); - printk_debug("msr 0x%08X will be set to %08x:%08x\n", CPU_RCONF_DEFAULT, msr.hi, msr.lo); + printk(BIOS_DEBUG, "msr 0x%08X will be set to %08x:%08x\n", CPU_RCONF_DEFAULT, msr.hi, msr.lo); wrmsr(CPU_RCONF_DEFAULT, msr); enable_cache(); @@ -214,7 +214,7 @@ setup_gx2(void) #if 0 /* This has already been done elsewhere */ - printk_debug("size_kb 0x%x, membytes 0x%x\n", size_kb, membytes); + printk(BIOS_DEBUG, "size_kb 0x%x, membytes 0x%x\n", size_kb, membytes); msr.hi = 0x20000000 | membytes>>24; msr.lo = 0x100 | ( ((membytes >>12) & 0xfff) << 20); wrmsr(0x10000028, msr); @@ -224,9 +224,9 @@ setup_gx2(void) #endif #if 0 msr = rdmsr(0x10000028); - printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi,msr.lo); + printk(BIOS_DEBUG, "MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi,msr.lo); msr = rdmsr(0x40000029); - printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi,msr.lo); + printk(BIOS_DEBUG, "MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi,msr.lo); #endif #if 1 /* fixme: SMM MSR 0x10000026 and 0x400000023 */ @@ -240,7 +240,7 @@ setup_gx2(void) /* calculate the PBASE and PMASK fields */ tmp2 = (SMM_OFFSET << 8) & 0xFFF00000; /* shift right 12 then left 20 == left 8 */ tmp2 |= (((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff); - printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, tmp, tmp2); + printk(BIOS_DEBUG, "MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, tmp, tmp2); msr.hi = tmp; msr.lo = tmp2; wrmsr(0x10000026, msr); @@ -251,14 +251,14 @@ setup_gx2(void) msr.lo = 0x400fffc0; wrmsr(0x10000026, msr); msr = rdmsr(0x10000026); - printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, msr.hi, msr.lo); + printk(BIOS_DEBUG, "MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, msr.hi, msr.lo); #endif #if 0 msr.hi = 0x22fffc02; msr.lo = 0x10ffbf00; wrmsr(0x1808, msr); msr = rdmsr(0x1808); - printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x1808, msr.hi, msr.lo); + printk(BIOS_DEBUG, "MSR 0x%x is now 0x%x:0x%x\n", 0x1808, msr.hi, msr.lo); #endif #if 0 // SDG - don't do this /* now do the default MSR values */ @@ -266,7 +266,7 @@ setup_gx2(void) msr_t msr; wrmsr(msr_defaults[i].msr_no, msr_defaults[i].msr); // MSR - see table above msr = rdmsr(msr_defaults[i].msr_no); - printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", msr_defaults[i].msr_no, msr.hi,msr.lo); + printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", msr_defaults[i].msr_no, msr.hi,msr.lo); } #endif } @@ -281,7 +281,7 @@ static void northbridge_init(device_t dev) unsigned long m; struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info; - printk_debug("northbridge: %s()\n", __func__); + printk(BIOS_DEBUG, "northbridge: %s()\n", __func__); enable_shadow(dev); irq_init_steering(dev, nb->irqmap); @@ -429,10 +429,10 @@ static void pci_domain_set_resources(device_t dev) *bcdramtop = ((tomk << 10) - 1); *mcgbaseadd = (tomk >> 9); - printk_debug("BC_DRAM_TOP = 0x%08x\n", *bcdramtop); - printk_debug("MC_GBASE_ADD = 0x%08x\n", *mcgbaseadd); + printk(BIOS_DEBUG, "BC_DRAM_TOP = 0x%08x\n", *bcdramtop); + printk(BIOS_DEBUG, "MC_GBASE_ADD = 0x%08x\n", *mcgbaseadd); - printk_debug("I would set ram size to %d Mbytes\n", (tomk >> 10)); + printk(BIOS_DEBUG, "I would set ram size to %d Mbytes\n", (tomk >> 10)); /* Compute the top of Low memory */ tolmk = pci_tolm >> 10; @@ -483,7 +483,7 @@ extern uint64_t high_tables_base, high_tables_size; static void enable_dev(struct device *dev) { - printk_debug("gx2 north: enable_dev\n"); + printk(BIOS_DEBUG, "gx2 north: enable_dev\n"); void northbridgeinit(void); void chipsetinit(struct northbridge_amd_gx2_config *nb); void do_vsmbios(void); @@ -492,7 +492,7 @@ static void enable_dev(struct device *dev) struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info; extern void cpubug(void); u32 tomk; - printk_debug("DEVICE_PATH_PCI_DOMAIN\n"); + printk(BIOS_DEBUG, "DEVICE_PATH_PCI_DOMAIN\n"); /* cpubug MUST be called before setup_gx2(), so we force the issue here */ northbridgeinit(); cpubug(); @@ -510,10 +510,10 @@ static void enable_dev(struct device *dev) #endif ram_resource(dev, 0, 0, tomk); } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { - printk_debug("DEVICE_PATH_APIC_CLUSTER\n"); + printk(BIOS_DEBUG, "DEVICE_PATH_APIC_CLUSTER\n"); dev->ops = &cpu_bus_ops; } - printk_debug("gx2 north: end enable_dev\n"); + printk(BIOS_DEBUG, "gx2 north: end enable_dev\n"); } struct chip_operations northbridge_amd_gx2_ops = { diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c index 995c1f3212..491466577d 100644 --- a/src/northbridge/amd/gx2/northbridgeinit.c +++ b/src/northbridge/amd/gx2/northbridgeinit.c @@ -112,10 +112,10 @@ writeglmsr(struct gliutable *gl){ msr.lo = gl->lo; msr.hi = gl->hi; wrmsr(gl->desc_name, msr); // MSR - see table above - printk_debug("%s: write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); + printk(BIOS_DEBUG, "%s: write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); /* they do this, so we do this */ msr = rdmsr(gl->desc_name); - printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); + printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); } static void @@ -147,7 +147,7 @@ SysmemInit(struct gliutable *gl) * system. We will adjust for SMM and DMM now and Frame Buffer later. */ sizembytes = sizeram(); - printk_debug("%s: enable for %dm bytes\n", __func__, sizembytes); + printk(BIOS_DEBUG, "%s: enable for %dm bytes\n", __func__, sizembytes); sizebytes = sizembytes << 20; sizebytes -= SMM_SIZE*1024 +1; @@ -164,7 +164,7 @@ SysmemInit(struct gliutable *gl) msr.lo = sizebytes; wrmsr(gl->desc_name, msr); // MSR - see table above msr = rdmsr(gl->desc_name); - printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, + printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); } @@ -177,11 +177,11 @@ DMMGL0Init(struct gliutable *gl) { if (! havedmi) return; - printk_debug("%s: %d bytes\n", __func__, sizebytes); + printk(BIOS_DEBUG, "%s: %d bytes\n", __func__, sizebytes); sizebytes -= DMM_SIZE*1024; offset = sizebytes - DMM_OFFSET; - printk_debug("%s: offset is 0x%08x\n", __func__, offset); + printk(BIOS_DEBUG, "%s: offset is 0x%08x\n", __func__, offset); offset >>= 12; msr.hi = (gl->hi) | (offset << 8); /* I don't think this is needed */ @@ -192,7 +192,7 @@ DMMGL0Init(struct gliutable *gl) { wrmsr(gl->desc_name, msr); // MSR - See table above msr = rdmsr(gl->desc_name); - printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); + printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); } static void @@ -202,7 +202,7 @@ DMMGL1Init(struct gliutable *gl) { if (! havedmi) return; - printk_debug("%s:\n", __func__ ); + printk(BIOS_DEBUG, "%s:\n", __func__ ); msr.hi = gl->hi; /* I don't think this is needed */ @@ -210,12 +210,12 @@ DMMGL1Init(struct gliutable *gl) { msr.hi |= (DMM_OFFSET >> 24); msr.lo = DMM_OFFSET << 8; /* hmm. AMD source has SMM here ... SMM, not DMM? We think DMM */ - printk_err("%s: warning, using DMM_SIZE even though AMD used SMM_SIZE\n", __func__); + printk(BIOS_ERR, "%s: warning, using DMM_SIZE even though AMD used SMM_SIZE\n", __func__); msr.lo |= ((~(DMM_SIZE*1024)+1)>>12)&0xfffff; wrmsr(gl->desc_name, msr); // MSR - See table above msr = rdmsr(gl->desc_name); - printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); + printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); } static void SMMGL0Init(struct gliutable *gl) { @@ -228,10 +228,10 @@ SMMGL0Init(struct gliutable *gl) { if (havedmi) sizebytes -= DMM_SIZE * 1024; - printk_debug("%s: %d bytes\n", __func__, sizebytes); + printk(BIOS_DEBUG, "%s: %d bytes\n", __func__, sizebytes); offset = sizebytes - SMM_OFFSET; - printk_debug("%s: offset is 0x%08x\n", __func__, offset); + printk(BIOS_DEBUG, "%s: offset is 0x%08x\n", __func__, offset); offset >>= 12; msr.hi = offset << 8; @@ -242,12 +242,12 @@ SMMGL0Init(struct gliutable *gl) { wrmsr(gl->desc_name, msr); // MSR - See table above msr = rdmsr(gl->desc_name); - printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); + printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); } static void SMMGL1Init(struct gliutable *gl) { msr_t msr; - printk_debug("%s:\n", __func__ ); + printk(BIOS_DEBUG, "%s:\n", __func__ ); msr.hi = gl->hi; /* I don't think this is needed */ @@ -258,7 +258,7 @@ SMMGL1Init(struct gliutable *gl) { wrmsr(gl->desc_name, msr); // MSR - See table above msr = rdmsr(gl->desc_name); - printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); + printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); } static void @@ -350,7 +350,7 @@ static void GLPCIInit(void){ /* So we need a high page aligned addresss (pah) and low page aligned address (pal) * pah is from msr.hi << 12 | msr.low >> 20. pal is msr.lo << 12 */ - printk_debug("GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi); + printk(BIOS_DEBUG, "GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi); pah = ((msr.hi &0xff) << 12) | ((msr.lo >> 20) & 0xfff); /* we have the page address. Now make it a page-aligned address */ pah <<= 12; @@ -359,7 +359,7 @@ static void GLPCIInit(void){ msr.hi = pah; msr.lo = pal; msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET | GLPCI_RC_LOWER_WC_SET; - printk_debug("GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi); + printk(BIOS_DEBUG, "GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi); msrnum = GLPCI_RC1; wrmsr(msrnum, msr); } @@ -507,10 +507,10 @@ performance: for(i = 0; gating->msrnum != 0xffffffff; i++) { msr = rdmsr(gating->msrnum); - printk_debug("%s: MSR 0x%08x is 0x%08x:0x%08x\n", __func__, gating->msrnum, msr.hi, msr.lo); + printk(BIOS_DEBUG, "%s: MSR 0x%08x is 0x%08x:0x%08x\n", __func__, gating->msrnum, msr.hi, msr.lo); msr.hi |= gating->msr.hi; msr.lo |= gating->msr.lo; - printk_debug("%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __func__, + printk(BIOS_DEBUG, "%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __func__, gating->msrnum, msr.hi, msr.lo); wrmsr(gating->msrnum, msr); // MSR - See the table above gating +=1; @@ -526,11 +526,11 @@ GeodeLinkPriority(void){ for(i = 0; prio->msrnum != 0xffffffff; i++) { msr = rdmsr(prio->msrnum); - printk_debug("%s: MSR 0x%08x is 0x%08x:0x%08x\n", __func__, prio->msrnum, msr.hi, msr.lo); + printk(BIOS_DEBUG, "%s: MSR 0x%08x is 0x%08x:0x%08x\n", __func__, prio->msrnum, msr.hi, msr.lo); msr.hi |= prio->msr.hi; msr.lo &= ~0xfff; msr.lo |= prio->msr.lo; - printk_debug("%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __func__, + printk(BIOS_DEBUG, "%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __func__, prio->msrnum, msr.hi, msr.lo); wrmsr(prio->msrnum, msr); // MSR - See the table above prio +=1; @@ -772,7 +772,7 @@ northbridgeinit(void) { msr_t msr; int i; - printk_debug("Enter %s\n", __func__); + printk(BIOS_DEBUG, "Enter %s\n", __func__); for(i = 0; gliutables[i]; i++) GLIUInit(gliutables[i]); @@ -803,6 +803,6 @@ northbridgeinit(void) ClockGatingInit(); __asm__("FINIT\n"); /* CPUBugsFix -- called elsewhere */ - printk_debug("Exit %s\n", __func__); + printk(BIOS_DEBUG, "Exit %s\n", __func__); } -- cgit v1.2.3