From 76890dde1428741a7c91732b04cc3c95ada9c321 Mon Sep 17 00:00:00 2001 From: Nils Jacobs Date: Mon, 1 Nov 2010 15:20:27 +0000 Subject: Change Geode GX2 to use the auto DRAM detect code from Geode LX. Also, change the GX2 boards to use it. Add a processor speed setting function in human readable MHz and remove the useless and broken PLLMSR settings (the processor speed was hardcoded to 366MHz in pll_reset.c). Signed-off-by: Nils Jacobs Acked-by: Uwe Hermann git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6011 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/northbridge/amd/gx2/pll_reset.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) (limited to 'src/northbridge/amd/gx2/pll_reset.c') diff --git a/src/northbridge/amd/gx2/pll_reset.c b/src/northbridge/amd/gx2/pll_reset.c index f9e780cb61..81cc28d9c8 100644 --- a/src/northbridge/amd/gx2/pll_reset.c +++ b/src/northbridge/amd/gx2/pll_reset.c @@ -63,13 +63,25 @@ static const unsigned char fbdiv2plldiv[] = { #define DEFAULT_MDIV 3 #define DEFAULT_VDIV 2 -#define DEFAULT_FBDIV 22 // 366/244 ; 24 400/266 018 ;300/200 static void pll_reset(void) { msr_t msrGlcpSysRstpll; unsigned MDIV_VDIV_FBDIV; unsigned SyncBits; /* store the sync bits in up ebx */ + unsigned DEFAULT_FBDIV; + + if (CONFIG_PROCESSOR_MHZ == 400) { + DEFAULT_FBDIV = 24; + } else if (CONFIG_PROCESSOR_MHZ == 366) { + DEFAULT_FBDIV = 22; + } else if (CONFIG_PROCESSOR_MHZ == 300) { + DEFAULT_FBDIV = 18; + } else { + printk(BIOS_ERR, "Unsupported PROCESSOR_MHZ setting!\n"); + post_code(POST_PLL_CPU_VER_FAIL); + __asm__ __volatile__("hlt\n"); + } /* clear the Bypass bit */ @@ -179,3 +191,10 @@ static void pll_reset(void) } /* we haven't configured the PLL; do it now */ } + +static unsigned int GeodeLinkSpeed(void) +{ + unsigned geodelinkspeed; + geodelinkspeed = ((CONFIG_PROCESSOR_MHZ * DEFAULT_VDIV) / DEFAULT_MDIV); + return (geodelinkspeed); +} -- cgit v1.2.3