From 1c6d4e605588c03edf4e7ab70056d7c075fc5bb1 Mon Sep 17 00:00:00 2001 From: Nils Jacobs Date: Sun, 26 Dec 2010 05:12:49 +0000 Subject: Clean up Geode GX2 comments, whitespace and coding style. Trivial. Signed-off-by: Nils Jacobs Acked-by: Patrick Georgi Acked-by: Peter Stuge git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6208 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/northbridge/amd/gx2/northbridgeinit.c | 117 ++++++++++++++---------------- 1 file changed, 55 insertions(+), 62 deletions(-) (limited to 'src/northbridge/amd/gx2/northbridgeinit.c') diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c index 410998a70f..446c1e79cf 100644 --- a/src/northbridge/amd/gx2/northbridgeinit.c +++ b/src/northbridge/amd/gx2/northbridgeinit.c @@ -15,38 +15,40 @@ /* put this here for now, we are not sure where it belongs */ -struct gliutable { +struct gliutable +{ unsigned long desc_name; unsigned short desc_type; unsigned long hi, lo; }; struct gliutable gliu0table[] = { - {.desc_name=MSR_GLIU0_BASE1, .desc_type= BM,.hi= MSR_MC + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */ + {.desc_name=MSR_GLIU0_BASE1, .desc_type= BM,.hi= MSR_MC + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */ {.desc_name=MSR_GLIU0_BASE2, .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc */ - {.desc_name=MSR_GLIU0_SHADOW, .desc_type= SC_SHADOW,.hi= MSR_MC + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */ - {.desc_name=MSR_GLIU0_SYSMEM, .desc_type= R_SYSMEM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */ - {.desc_name=MSR_GLIU0_DMM, .desc_type= BMO_DMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */ - {.desc_name=MSR_GLIU0_SMM, .desc_type= BMO_SMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */ + {.desc_name=MSR_GLIU0_SHADOW, .desc_type= SC_SHADOW,.hi= MSR_MC + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */ + {.desc_name=MSR_GLIU0_SYSMEM, .desc_type= R_SYSMEM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */ + {.desc_name=MSR_GLIU0_DMM, .desc_type= BMO_DMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */ + {.desc_name=MSR_GLIU0_SMM, .desc_type= BMO_SMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */ {.desc_name=GLIU0_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU}, {.desc_name=GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0}, }; struct gliutable gliu1table[] = { - {.desc_name=MSR_GLIU1_BASE1,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */ + {.desc_name=MSR_GLIU1_BASE1,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */ {.desc_name=MSR_GLIU1_BASE2,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= (0x80 << 20) +0x0FFFE0}, /* 80000-9ffff to Mc */ - {.desc_name=MSR_GLIU1_SHADOW,.desc_type= SC_SHADOW,.hi= MSR_GL0 + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) */ - {.desc_name=MSR_GLIU1_SYSMEM,.desc_type= R_SYSMEM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */ - {.desc_name=MSR_GLIU1_DMM,.desc_type= BM_DMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */ - {.desc_name=MSR_GLIU1_SMM,.desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */ + {.desc_name=MSR_GLIU1_SHADOW,.desc_type= SC_SHADOW,.hi= MSR_GL0 + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) */ + {.desc_name=MSR_GLIU1_SYSMEM,.desc_type= R_SYSMEM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */ + {.desc_name=MSR_GLIU1_DMM,.desc_type= BM_DMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */ + {.desc_name=MSR_GLIU1_SMM,.desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */ {.desc_name=GLIU1_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0}, - {.desc_name=MSR_GLIU1_FPU_TRAP,.desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0}, /* FooGlue FPU 0xF0 */ + {.desc_name=MSR_GLIU1_FPU_TRAP,.desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0}, /* FooGlue FPU 0xF0 */ {.desc_name=GL_END,.desc_type= GL_END,.hi= 0x0,.lo= 0x0}, }; struct gliutable *gliutables[] = {gliu0table, gliu1table, 0}; -struct msrinit { +struct msrinit +{ unsigned long msrnum; msr_t msr; }; @@ -56,15 +58,16 @@ struct msrinit ClockGatingDefault [] = { /* MC must stay off in SDR mode. It is turned on in CPUBug??? lotus #77.142 */ {MC_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, {GLIU1_GLD_MSR_PM, {.hi=0x00,.lo=0x0005}}, - {VG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* lotus #77.163 */ + {VG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* lotus #77.163 */ {GP_GLD_MSR_PM, {.hi=0x00,.lo=0x0001}}, {DF_GLD_MSR_PM, {.hi=0x00,.lo=0x0155}}, {GLCP_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}}, {GLPCI_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}}, - {FG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* Always on */ + {FG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* Always on */ {0xffffffff, {0xffffffff, 0xffffffff}}, }; - /* All On */ + +/* All On */ struct msrinit ClockGatingAllOn[] = { {GLIU0_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}}, {MC_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}}, @@ -78,16 +81,16 @@ struct msrinit ClockGatingAllOn[] = { {0xffffffff, {0xffffffff, 0xffffffff}}, }; - /* Performance */ +/* Performance */ struct msrinit ClockGatingPerformance[] = { - {VG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* lotus #77.163*/ + {VG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* lotus #77.163 */ {GP_GLD_MSR_PM, {.hi=0x00,.lo=0x0001}}, {DF_GLD_MSR_PM, {.hi=0x00,.lo=0x0155}}, {GLCP_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}}, {0xffffffff, {0xffffffff, 0xffffffff}}, }; - /* SET GeodeLink PRIORITY */ +/* SET GeodeLink PRIORITY */ struct msrinit GeodeLinkPriorityTable [] = { {CPU_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0220}}, /* CPU Priority. */ {DF_GLD_MSR_MASTER_CONF, {.hi=0x00,.lo=0x0000}}, /* DF Priority. */ @@ -103,8 +106,8 @@ struct msrinit GeodeLinkPriorityTable [] = { /* do we have dmi or not? assume NO per AMD */ int havedmi = 0; -static void -writeglmsr(struct gliutable *gl){ +static void writeglmsr(struct gliutable *gl) +{ msr_t msr; msr.lo = gl->lo; @@ -116,8 +119,7 @@ writeglmsr(struct gliutable *gl){ printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); } -static void -ShadowInit(struct gliutable *gl) +static void ShadowInit(struct gliutable *gl) { msr_t msr; @@ -132,14 +134,12 @@ ShadowInit(struct gliutable *gl) * CLEAN ME UP */ /* yes, this duplicates later code, but it seems that is how they want it done. */ -static void -SysmemInit(struct gliutable *gl) +static void SysmemInit(struct gliutable *gl) { msr_t msr; int sizembytes, sizebytes; - /* - * Figure out how much RAM is in the machine and alocate all to the + /* Figure out how much RAM is in the machine and alocate all to the * system. We will adjust for SMM and DMM now and Frame Buffer later. */ sizembytes = sizeram(); @@ -164,8 +164,8 @@ SysmemInit(struct gliutable *gl) gl->desc_name, msr.hi, msr.lo); } -static void -DMMGL0Init(struct gliutable *gl) { +static void DMMGL0Init(struct gliutable *gl) +{ msr_t msr; int sizebytes = sizeram()<<20; long offset; @@ -191,8 +191,8 @@ DMMGL0Init(struct gliutable *gl) { printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); } -static void -DMMGL1Init(struct gliutable *gl) { +static void DMMGL1Init(struct gliutable *gl) +{ msr_t msr; if (! havedmi) @@ -214,8 +214,8 @@ DMMGL1Init(struct gliutable *gl) { printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); } -static void -SMMGL0Init(struct gliutable *gl) { +static void SMMGL0Init(struct gliutable *gl) +{ msr_t msr; int sizebytes = sizeram()<<20; long offset; @@ -242,8 +242,8 @@ SMMGL0Init(struct gliutable *gl) { printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); } -static void -SMMGL1Init(struct gliutable *gl) { +static void SMMGL1Init(struct gliutable *gl) +{ msr_t msr; printk(BIOS_DEBUG, "%s:\n", __func__ ); @@ -259,9 +259,8 @@ SMMGL1Init(struct gliutable *gl) { printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); } -static void -GLIUInit(struct gliutable *gl){ - +static void GLIUInit(struct gliutable *gl) +{ while (gl->desc_type != GL_END){ switch(gl->desc_type){ default: @@ -295,8 +294,7 @@ GLIUInit(struct gliutable *gl){ } } -/* - * Set up GLPCI settings for reads/write into memory. +/* Set up GLPCI settings for reads/write into memory. * * R0: 0-640KB, * R1: 1MB - Top of System Memory @@ -304,7 +302,8 @@ GLIUInit(struct gliutable *gl){ * R3: Framebuffer? - not set up yet * R4: ?? */ -static void GLPCIInit(void){ +static void GLPCIInit(void) +{ struct gliutable *gl = 0; int i; msr_t msr; @@ -334,7 +333,7 @@ static void GLPCIInit(void){ * base of 1M and top of around 256M */ /* we have to create a page-aligned (4KB page) address for base and top - * So we need a high page aligned addresss (pah) and low page aligned address (pal) + * so we need a high page aligned addresss (pah) and low page aligned address (pal) * pah is from msr.hi << 12 | msr.low >> 20. pal is msr.lo << 12 */ printk(BIOS_DEBUG, "GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi); @@ -504,8 +503,7 @@ static void GeodeLinkPriority(void) } } -/* - * Get the GLIU0 shadow register settings. +/* Get the GLIU0 shadow register settings. * * If the setShadow function is used then all shadow descriptors * will stay sync'ed. @@ -517,8 +515,7 @@ static uint64_t getShadow(void) return ( ( (uint64_t) msr.hi ) << 32 ) | msr.lo; } -/* - * Set the cache RConf registers for the memory hole. +/* Set the cache RConf registers for the memory hole. * * Keeps all cache shadow descriptors sync'ed. * This is part of the PCI lockup solution. @@ -536,17 +533,17 @@ static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo) /* load up D000 settings in edx. */ for (bit = 8; (bit > 4); bit--) { msr.hi <<= 8; - msr.hi |= 1; /* cache disable PCI/Shadow memory */ + msr.hi |= 1; /* cache disable PCI/Shadow memory */ if (shadowByte && (1 << bit)) - msr.hi |= 0x20; /* write serialize PCI memory */ + msr.hi |= 0x20; /* write serialize PCI memory */ } /* load up C000 settings in eax. */ for ( ; bit; bit--) { msr.lo <<= 8; - msr.lo |= 1; /* cache disable PCI/Shadow memory */ + msr.lo |= 1; /* cache disable PCI/Shadow memory */ if (shadowByte && (1 << bit)) - msr.lo |= 0x20; /* write serialize PCI memory */ + msr.lo |= 0x20; /* write serialize PCI memory */ } wrmsr(CPU_RCONF_C0_DF, msr); @@ -556,24 +553,23 @@ static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo) /* load up F000 settings in edx. */ for (bit = 8; (bit > 4); bit--) { msr.hi <<= 8; - msr.hi |= 1; /* cache disable PCI/Shadow memory */ + msr.hi |= 1; /* cache disable PCI/Shadow memory */ if (shadowByte && (1 << bit)) - msr.hi |= 0x20; /* write serialize PCI memory */ + msr.hi |= 0x20; /* write serialize PCI memory */ } /* load up E000 settings in eax. */ for ( ; bit; bit--) { msr.lo <<= 8; - msr.lo |= 1; /* cache disable PCI/Shadow memory */ + msr.lo |= 1; /* cache disable PCI/Shadow memory */ if (shadowByte && (1 << bit)) - msr.lo |= 0x20; /* write serialize PCI memory */ + msr.lo |= 0x20; /* write serialize PCI memory */ } wrmsr(CPU_RCONF_E0_FF, msr); } -/* - * Set the GLPCI registers for the memory hole. +/* Set the GLPCI registers for the memory hole. * Keeps all cache shadow descriptors sync'ed. * Entry: EDX:EAX is the shadow settings */ @@ -588,8 +584,7 @@ static void setShadowGLPCI(uint32_t shadowHi, uint32_t shadowLo) wrmsr(GLPCI_REN, msr); } -/* - * Set the GLIU SC register settings. Scans descriptor tables for SC_SHADOW. +/* Set the GLIU SC register settings. Scans descriptor tables for SC_SHADOW. * Keeps all shadow descriptors sync'ed. * Entry: EDX:EAX is the shadow settings */ @@ -630,8 +625,7 @@ static void shadowRom(void) setShadow(shadowSettings); } -/* - * Set up RCONF_DEFAULT and any other RCONF registers needed. +/* Set up RCONF_DEFAULT and any other RCONF registers needed. * * DEVRC_RCONF_DEFAULT: * ROMRC(63:56) = 04h ; write protect ROMBASE @@ -645,8 +639,7 @@ static void shadowRom(void) #define ROMBASE_RCONF_DEFAULT 0xFFFC0000 #define ROMRC_RCONF_DEFAULT 0x25 -static void -RCONFInit(void) +static void RCONFInit(void) { struct gliutable *gl = 0; int i; -- cgit v1.2.3