From f7741d7964e3cd91d60f950dc78550999995bca0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 24 May 2018 09:56:04 +0300 Subject: Remove leftover AMD CIMX RD890 northbridge support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I3f2cea79a11a52e94f479b25f22eb3726af38fa3 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/26507 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/northbridge/amd/cimx/Kconfig | 20 -- src/northbridge/amd/cimx/Makefile.inc | 20 -- src/northbridge/amd/cimx/rd890/Kconfig | 32 --- src/northbridge/amd/cimx/rd890/Makefile.inc | 20 -- src/northbridge/amd/cimx/rd890/NbPlatform.h | 133 ---------- src/northbridge/amd/cimx/rd890/amd.h | 377 ---------------------------- src/northbridge/amd/cimx/rd890/chip.h | 30 --- src/northbridge/amd/cimx/rd890/early.c | 109 -------- src/northbridge/amd/cimx/rd890/late.c | 172 ------------- src/northbridge/amd/cimx/rd890/nb_cimx.h | 39 --- 10 files changed, 952 deletions(-) delete mode 100644 src/northbridge/amd/cimx/Kconfig delete mode 100644 src/northbridge/amd/cimx/Makefile.inc delete mode 100644 src/northbridge/amd/cimx/rd890/Kconfig delete mode 100644 src/northbridge/amd/cimx/rd890/Makefile.inc delete mode 100644 src/northbridge/amd/cimx/rd890/NbPlatform.h delete mode 100644 src/northbridge/amd/cimx/rd890/amd.h delete mode 100644 src/northbridge/amd/cimx/rd890/chip.h delete mode 100644 src/northbridge/amd/cimx/rd890/early.c delete mode 100644 src/northbridge/amd/cimx/rd890/late.c delete mode 100644 src/northbridge/amd/cimx/rd890/nb_cimx.h (limited to 'src/northbridge/amd/cimx') diff --git a/src/northbridge/amd/cimx/Kconfig b/src/northbridge/amd/cimx/Kconfig deleted file mode 100644 index d37418088a..0000000000 --- a/src/northbridge/amd/cimx/Kconfig +++ /dev/null @@ -1,20 +0,0 @@ -# -# This file is part of the coreboot project. -# -#Copyright (C) 2012 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -config AMD_NB_CIMX - bool - default n - -source src/northbridge/amd/cimx/rd890/Kconfig diff --git a/src/northbridge/amd/cimx/Makefile.inc b/src/northbridge/amd/cimx/Makefile.inc deleted file mode 100644 index c695108077..0000000000 --- a/src/northbridge/amd/cimx/Makefile.inc +++ /dev/null @@ -1,20 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -ifeq ($(CONFIG_AMD_NB_CIMX),y) - -subdirs-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890 - -endif diff --git a/src/northbridge/amd/cimx/rd890/Kconfig b/src/northbridge/amd/cimx/rd890/Kconfig deleted file mode 100644 index a83a34fc38..0000000000 --- a/src/northbridge/amd/cimx/rd890/Kconfig +++ /dev/null @@ -1,32 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -config NORTHBRIDGE_AMD_CIMX_RD890 - bool - default n - select AMD_NB_CIMX - -if NORTHBRIDGE_AMD_CIMX_RD890 - -config REDIRECT_NBCIMX_TRACE_TO_SERIAL - bool "Redirect AMD Northbridge CIMX Trace to serial console" - default n - help - This Option allows you to redirect the AMD Northbridge CIMX - Trace debug information to the serial console. - - Warning: Only enable this option when debuging or tracing AMD CIMX code. - -endif # NORTHBRIDGE_AMD_CIMX_RD890 diff --git a/src/northbridge/amd/cimx/rd890/Makefile.inc b/src/northbridge/amd/cimx/rd890/Makefile.inc deleted file mode 100644 index 4704876621..0000000000 --- a/src/northbridge/amd/cimx/rd890/Makefile.inc +++ /dev/null @@ -1,20 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - - -# RD890 Platform Files -romstage-y += early.c - -ramstage-y += late.c diff --git a/src/northbridge/amd/cimx/rd890/NbPlatform.h b/src/northbridge/amd/cimx/rd890/NbPlatform.h deleted file mode 100644 index 1a8c40e0cb..0000000000 --- a/src/northbridge/amd/cimx/rd890/NbPlatform.h +++ /dev/null @@ -1,133 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _NB_PLATFORM_H_ -#define _NB_PLATFORM_H_ - -#define SERIAL_OUT_SUPPORT //enable serial output -#define CIMX_DEBUG - -#ifdef CIMX_DEBUG -#define CIMX_TRACE_SUPPORT -#define CIMX_ASSERT_SUPPORT -#endif - -#ifdef CIMX_TRACE_SUPPORT - #define CIMX_INIT_TRACE(Arguments) - #if IS_ENABLED(CONFIG_REDIRECT_NBCIMX_TRACE_TO_SERIAL) - #define TRACE_DATA(Ptr, Level) BIOS_DEBUG //always enable - #define CIMX_TRACE(Argument) do {do_printk Argument;} while (0) - #else - #define TRACE_DATA(Ptr, Level) - #define CIMX_TRACE(Argument) - #endif -#else - #define CIMX_TRACE(Argument) - #define CIMX_INIT_TRACE(Arguments) -#endif - -#ifdef CIMX_ASSERT_SUPPORT - #ifdef ASSERT - #undef ASSERT - #define ASSERT CIMX_ASSERT - #endif - #ifdef CIMX_TRACE_SUPPORT - #define CIMX_ASSERT(x) if (!(x)) {\ - LibAmdTraceDebug (CIMX_TRACE_ALL, (CHAR8 *)"ASSERT !!! "__FILE__" - line %d\n", __LINE__); \ - /*__asm {jmp $}; */\ - } - //#define IDS_HDT_CONSOLE(s, args...) do_printk(BIOS_DEBUG, s, ##args) - #else - #define CIMX_ASSERT(x) if (!(x)) {\ - /*__asm {jmp $}; */\ - } - #endif -#else - #define CIMX_ASSERT(x) -#endif - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -//#define STALL(Ptr, TimeUs, Flag) LibAmdSbStall(TimeUs) -#define STALL(Ptr, TimeUs, Flag) LibAmdSbStall(TimeUs, Ptr) - -#define REPORT_EVENT(Class, Info, Param1, Param2, Param3, Param4, CfgPtr) - -// CIMX configuration parameters -/* - * PCIEX_BASE_ADDRESS - Define PCIE base address - */ -#ifdef MOVE_PCIEBAR_TO_F0000000 -#define PCIEX_BASE_ADDRESS 0xF7000000 -#else -#define PCIEX_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS -#endif - - - -#define CIMX_S3_SAVE 1 -#include "cbtypes.h" -#include - -#include "amd.h" //cimx typedef -#include -#include "amdAcpiLib.h" -#include "amdAcpiMadt.h" -#include "amdAcpiIvrs.h" -#include "amdSbLib.h" -#include "nbPcie.h" - -//must put before the nbType.h -#include "platform_cfg.h" /*platform dependented configuration */ -#include "nbType.h" - -#include "nbLib.h" -#include "nbDef.h" -#include "nbInit.h" -#include "nbHtInit.h" -#include "nbIommu.h" -#include "nbEventLog.h" -#include "nbRegisters.h" -#include "nbPcieAspm.h" -#include "nbPcieLinkWidth.h" -#include "nbPcieHotplug.h" -#include "nbPciePortRemap.h" -#include "nbPcieWorkarounds.h" -#include "nbPcieCplBuffers.h" -#include "nbPciePllControl.h" -#include "nbMiscInit.h" -#include "nbIoApic.h" -#include "nbPcieSb.h" -#include "nbRecovery.h" -#include "nbMaskedMemoryInit.h" - - -#define FIX_PTR_ADDR(x, y) x - -#define TRACE_ALWAYS 0xffffffff - -#define AmdNbDispatcher NULL - -#define CIMX_TRACE_ALL 0xFFFFFFFF -#define CIMX_NBPOR_TRACE 0xFFFFFFFF -#define CIMX_NBHT_TRACE 0xFFFFFFFF -#define CIMX_NBPCIE_TRACE 0xFFFFFFFF -#define CIMX_NB_TRACE 0xFFFFFFFF -#define CIMX_NBPCIE_MISC 0xFFFFFFFF - -#endif diff --git a/src/northbridge/amd/cimx/rd890/amd.h b/src/northbridge/amd/cimx/rd890/amd.h deleted file mode 100644 index 898966df6c..0000000000 --- a/src/northbridge/amd/cimx/rd890/amd.h +++ /dev/null @@ -1,377 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _AMD_H_ -#define _AMD_H_ - -#include "cbtypes.h" - -#define VOLATILE volatile -#define CALLCONV -#define ROMDATA -#define CIMXAPI EFIAPI - -// -// -// AGESA Types and Definitions -// -// -#include - -#define LAST_ENTRY 0xFFFFFFFF -#define IOCF8 0xCF8 -#define IOCFC 0xCFC -#define IN -#define OUT -#define IMAGE_SIGNATURE 'DMA$' - -typedef UINT32 AGESA_STATUS; - - -#define AGESA_SUCCESS ((AGESA_STATUS) 0x0) -#define AGESA_ALERT ((AGESA_STATUS) 0x40000000) -#define AGESA_WARNING ((AGESA_STATUS) 0x40000001) -#define AGESA_UNSUPPORTED ((AGESA_STATUS) 0x80000003) -#define AGESA_ERROR ((AGESA_STATUS) 0xC0000001) -#define AGESA_CRITICAL ((AGESA_STATUS) 0xC0000002) -#define AGESA_FATAL ((AGESA_STATUS) 0xC0000003) - -typedef AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr); -typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT VOID* ConfigPtr); -typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT VOID* ConfigPtr); - -///This allocation type is used by the AmdCreateStruct entry point -typedef enum { - PreMemHeap = 0, ///< Create heap in cache. - PostMemDram, ///< Create heap in memory. - ByHost ///< Create heap by Host. -} ALLOCATION_METHOD; - -/// These width descriptors are used by the library function, and others, to specify the data size -typedef enum ACCESS_WIDTH { - AccessWidth8 = 1, ///< Access width is 8 bits. - AccessWidth16, ///< Access width is 16 bits. - AccessWidth32, ///< Access width is 32 bits. - AccessWidth64, ///< Access width is 64 bits. - - AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data. - AccessS3SaveWidth16, ///< Save 16 bits data. - AccessS3SaveWidth32, ///< Save 32 bits data. - AccessS3SaveWidth64, ///< Save 64 bits data. -} ACCESS_WIDTH; - - -// AGESA Structures -/// The standard header AMD NB UEFI drivers -typedef struct _AMD_CONFIG_PARAMS { - VOID **PeiServices; ///< Pointer to PEI service table - VOID *StallPpi; ///< Pointer to Stall PPI -// UINT32 Func; - VOID *PcieBasePtr; ///< TBD - CALLOUT_ENTRY CalloutPtr; /// -#include "NbPlatform.h" -#include "rd890_cfg.h" -#include "nb_cimx.h" - - -/** - * @brief disable GPP1 Port0,1, GPP2, GPP3a Port0,1,2,3,4,5, GPP3b - * - * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, - * Disable all Pcie Bridges to work around It. - */ -void sr56x0_rd890_disable_pcie_bridge(void) -{ - u32 nb_dev; - u32 mask; - u32 val; - AMD_NB_CONFIG_BLOCK cfg_block; - AMD_NB_CONFIG_BLOCK *cfg_ptr = &cfg_block; - AMD_NB_CONFIG *nb_cfg = &(cfg_block.Northbridges[0]); - - nb_cfg->ConfigPtr = &cfg_ptr; - nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); - val = (1 << 2) | (1 << 3); /*GPP1*/ - val |= (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | (1 << 16) | (1 << 17); /*GPP3a*/ - val |= (1 << 18) | (1 << 19); /*GPP2*/ - val |= (1 << 20); /*GPP3b*/ - mask = ~val; - LibNbPciIndexRMW(nb_dev | NB_MISC_INDEX, NB_MISC_REG0C, - AccessS3SaveWidth32, - mask, - val, - nb_cfg); -} - - -/** - * @brief South Bridge CIMx romstage entry, - * wrapper of AmdPowerOnResetInit entry point. - */ -void nb_Poweron_Init(void) -{ - NB_CONFIG nb_cfg[MAX_NB_COUNT]; - HT_CONFIG ht_cfg[MAX_NB_COUNT]; - PCIE_CONFIG pcie_cfg[MAX_NB_COUNT]; - AMD_NB_CONFIG_BLOCK gConfig; - AMD_NB_CONFIG_BLOCK *ConfigPtr = &gConfig; - AGESA_STATUS status; - - printk(BIOS_DEBUG, "cimx/rd890 early.c %s() Start\n", __func__); - CIMX_INIT_TRACE(); - CIMX_TRACE((BIOS_DEBUG, "NbPowerOnResetInit entry\n")); - rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); - - if (ConfigPtr->StandardHeader.CalloutPtr != NULL) { - ConfigPtr->StandardHeader.CalloutPtr(CB_AmdSetNbPorConfig, 0, &gConfig); - } - - status = AmdPowerOnResetInit(&gConfig); - printk(BIOS_DEBUG, "cimx/rd890 early.c %s() End. return status=%x\n", __func__, status); -} - -/** - * @brief South Bridge CIMx romstage entry, - * wrapper of AmdHtInit entry point. - */ -void nb_Ht_Init(void) -{ - AGESA_STATUS status; - NB_CONFIG nb_cfg[MAX_NB_COUNT]; - HT_CONFIG ht_cfg[MAX_NB_COUNT]; - PCIE_CONFIG pcie_cfg[MAX_NB_COUNT]; - AMD_NB_CONFIG_BLOCK gConfig; - AMD_NB_CONFIG_BLOCK *ConfigPtr = &gConfig; - u32 i; - - rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); - - //Initialize HT structure - LibSystemApiCall(AmdHtInitializer, &gConfig); - for (i = 0; i < MAX_NB_COUNT; i ++) { - if (ConfigPtr->StandardHeader.CalloutPtr != NULL) { - ConfigPtr->StandardHeader.CalloutPtr(CB_AmdSetHtConfig, 0, (VOID*)&(gConfig.Northbridges[i])); - } - } - - status = LibSystemApiCall(AmdHtInit, &gConfig); - printk(BIOS_DEBUG, "AmdHtInit status: %x\n", status); -} - -void nb_S3_Init(void) -{ - //TODO -} diff --git a/src/northbridge/amd/cimx/rd890/late.c b/src/northbridge/amd/cimx/rd890/late.c deleted file mode 100644 index 9581527a44..0000000000 --- a/src/northbridge/amd/cimx/rd890/late.c +++ /dev/null @@ -1,172 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include "NbPlatform.h" -#include "nb_cimx.h" -#include "rd890_cfg.h" - - -/** - * Global RD890 CIMX Configuration structure - */ -static NB_CONFIG nb_cfg[MAX_NB_COUNT]; -static HT_CONFIG ht_cfg[MAX_NB_COUNT]; -static PCIE_CONFIG pcie_cfg[MAX_NB_COUNT]; -static AMD_NB_CONFIG_BLOCK gConfig; - - -/** - * Reset PCIE Cores, Training the Ports selected by port_enable of devicetree - * After this call EP are fully operational on particular NB - */ -void nb_Pcie_Early_Init(void) -{ - LibSystemApiCall(AmdPcieEarlyInit, &gConfig); //AmdPcieEarlyInit(&gConfig); -} - -void nb_Pcie_Late_Init(void) -{ - LibSystemApiCall(AmdPcieLateInit, &gConfig); -} - -void nb_Early_Post_Init(void) -{ - LibSystemApiCall(AmdEarlyPostInit, &gConfig); -} - -void nb_Mid_Post_Init(void) -{ - LibSystemApiCall(AmdMidPostInit, &gConfig); -} - -void nb_Late_Post_Init(void) -{ - LibSystemApiCall(AmdLatePostInit, &gConfig); -} - -static void rd890_enable(device_t dev) -{ - u32 address = 0; - u32 devfn; - AMD_NB_CONFIG *NbConfigPtr = NULL; - - u8 nb_index = 0; /* The first IO Hub, TODO: other NBs */ - address = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); - NbConfigPtr = &(gConfig.Northbridges[nb_index]); - - devfn = dev->path.pci.devfn; - printk(BIOS_INFO, "rd890_enable "); - printk(BIOS_INFO, "Bus-%x Dev-%X Fun-%X, enable=%x\n", - 0, (devfn >> 3), (devfn & 0x07), dev->enabled); - - /* we only do this once */ - if (devfn == 0) { - /* CIMX configuration defualt initialize */ - rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); - if (gConfig.StandardHeader.CalloutPtr != NULL) { - gConfig.StandardHeader.CalloutPtr(CB_AmdSetPcieEarlyConfig, - (uintptr_t)dev, (VOID*)NbConfigPtr); - } - /* Reset PCIE Cores, Training the Ports selected by port_enable of devicetree - * After this call EP are fully operational on particular NB - */ - nb_Pcie_Early_Init(); - - if (gConfig.StandardHeader.CalloutPtr != NULL) { - gConfig.StandardHeader.CalloutPtr(CB_AmdSetEarlyPostConfig, 0, (VOID*)NbConfigPtr); - } - nb_Early_Post_Init(); - - if (gConfig.StandardHeader.CalloutPtr != NULL) { - gConfig.StandardHeader.CalloutPtr(CB_AmdSetMidPostConfig, 0, (VOID*)NbConfigPtr); - } - nb_Mid_Post_Init(); - nb_Pcie_Late_Init(); - - if (gConfig.StandardHeader.CalloutPtr != NULL) { - gConfig.StandardHeader.CalloutPtr(CB_AmdSetLatePostConfig, 0, (VOID*)NbConfigPtr); - } - nb_Late_Post_Init(); - } -} - -struct chip_operations northbridge_amd_cimx_rd890_ops = { - CHIP_NAME("ATI rd890") - .enable_dev = rd890_enable, -}; - - -static void ioapic_init(struct device *dev) -{ - void *ioapic_base; - - pci_write_config32(dev, 0xF8, 0x1); - ioapic_base = (void *)(uintptr_t)(pci_read_config32(dev, 0xFC) & 0xfffffff0); - clear_ioapic(ioapic_base); - setup_ioapic(ioapic_base, 1); -} - -static void rd890_read_resource(struct device *dev) -{ - pci_dev_read_resources(dev); - - /* rpr6.2.(1). Write the Base Address Register (BAR) */ - pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */ - pci_get_resource(dev, 0xFC); /* APIC located in sr5690 */ - - compact_resources(dev); -} - -/* If IOAPIC's index changes, we should replace the pci_dev_set_resource(). */ -static void rd890_set_resources(struct device *dev) -{ - pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */ - pci_dev_set_resources(dev); -} - -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - -static struct device_operations ht_ops = { - .read_resources = rd890_read_resource, - .set_resources = rd890_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ioapic_init, - .scan_bus = 0, - .ops_pci = &lops_pci, -}; - -static const unsigned short driver_ids[] = { - PCI_DEVICE_ID_AMD_SR5690_HT, - PCI_DEVICE_ID_AMD_SR5670_HT, - PCI_DEVICE_ID_AMD_SR5650_HT, - PCI_DEVICE_ID_AMD_RD890TV_HT, - PCI_DEVICE_ID_AMD_RD890_HT, - PCI_DEVICE_ID_AMD_990FX_HT, - 0 -}; - -static const struct pci_driver ht_driver_sr5690 __pci_driver = { - .ops = &ht_ops, - .vendor = PCI_VENDOR_ID_ATI, - .devices= driver_ids, -}; diff --git a/src/northbridge/amd/cimx/rd890/nb_cimx.h b/src/northbridge/amd/cimx/rd890/nb_cimx.h deleted file mode 100644 index 24f38db771..0000000000 --- a/src/northbridge/amd/cimx/rd890/nb_cimx.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _NB_CIMX_H_ -#define _NB_CIMX_H_ - -/** - * @brief disable GPP1 Port0,1, GPP2, GPP3a Port0,1,2,3,4,5, GPP3b - * - * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, - * Disable all Pcie Bridges to work around It. - */ -void sr56x0_rd890_disable_pcie_bridge(void); - -/** - * Northbridge CIMX entries point - */ -void nb_Poweron_Init(void); -void nb_Ht_Init(void); -void nb_S3_Init(void); -void nb_Early_Post_Init(void); -void nb_Mid_Post_Init(void); -void nb_Late_Post_Init(void); -void nb_Pcie_Early_Init(void); -void nb_Pcie_Late_Init(void); - -#endif /* _NB_CIMX_H_ */ -- cgit v1.2.3