From cd49cce7b70e80b4acc49b56bb2bb94370b4d867 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Tue, 5 Mar 2019 16:53:33 -0800 Subject: coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 12 +++++----- src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 6 ++--- src/northbridge/amd/amdmct/wrappers/mcti.h | 10 ++++---- src/northbridge/amd/amdmct/wrappers/mcti_d.c | 34 +++++++++++++-------------- 4 files changed, 31 insertions(+), 31 deletions(-) (limited to 'src/northbridge/amd/amdmct') diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 6f09b12a8a..9178c782d4 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -2620,7 +2620,7 @@ restartinit: mct_ForceNBPState0_En_Fam15(pMCTstat, pDCTstat); } -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if CONFIG(HAVE_ACPI_RESUME) printk(BIOS_DEBUG, "mctAutoInitMCT_D: Restoring DCT configuration from NVRAM\n"); if (restore_mct_information_from_nvram(0) != 0) printk(BIOS_CRIT, "%s: ERROR: Unable to restore DCT configuration from NVRAM\n", __func__); @@ -2692,11 +2692,11 @@ restartinit: nvram = 0; set_option("allow_spd_nvram_cache_restore", &nvram); -#if IS_ENABLED(CONFIG_DIMM_VOLTAGE_SET_SUPPORT) +#if CONFIG(DIMM_VOLTAGE_SET_SUPPORT) printk(BIOS_DEBUG, "%s: DIMMSetVoltage\n", __func__); DIMMSetVoltages(pMCTstat, pDCTstatA); /* Set the DIMM voltages (mainboard specific) */ #endif - if (!IS_ENABLED(CONFIG_DIMM_VOLTAGE_SET_SUPPORT)) { + if (!CONFIG(DIMM_VOLTAGE_SET_SUPPORT)) { /* Assume 1.5V operation */ for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { struct DCTStatStruc *pDCTstat; @@ -3674,7 +3674,7 @@ retry_dqs_training_and_levelization: mct_WriteLevelization_HW(pMCTstat, pDCTstatA, SecondPass); -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if CONFIG(HAVE_ACPI_RESUME) printk(BIOS_DEBUG, "mctAutoInitMCT_D: Restoring DIMM training configuration from NVRAM\n"); if (restore_mct_information_from_nvram(1) != 0) printk(BIOS_CRIT, "%s: ERROR: Unable to restore DCT configuration from NVRAM\n", __func__); @@ -5836,7 +5836,7 @@ static void mct_preInitDCT(struct MCTStatStruc *pMCTstat, } } -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if CONFIG(HAVE_ACPI_RESUME) calculate_and_store_spd_hashes(pMCTstat, pDCTstat); if (load_spd_hashes_from_nvram(pMCTstat, pDCTstat) < 0) { @@ -5853,7 +5853,7 @@ static void mct_preInitDCT(struct MCTStatStruc *pMCTstat, if (get_option(&nvram, "allow_spd_nvram_cache_restore") == CB_SUCCESS) allow_config_restore = !!nvram; -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if CONFIG(HAVE_ACPI_RESUME) if (pMCTstat->nvram_checksum != calculate_nvram_mct_hash()) allow_config_restore = 0; #else diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index 7267f12000..a78a752052 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -536,7 +536,7 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data *persistent_da data->f2x9cx0d0f812f = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f812f); /* Stage 11 */ - if (IS_ENABLED(CONFIG_DIMM_DDR3)) { + if (CONFIG(DIMM_DDR3)) { for (i = 0; i < 12; i++) data->f2x9cx30[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x30 + i); for (i = 0; i < 12; i++) @@ -654,7 +654,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data *persiste for (i = 0; i < 12; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x20 + i, data->f2x9cx20[i]); - if (IS_ENABLED(CONFIG_DIMM_DDR3)) { + if (CONFIG(DIMM_DDR3)) { for (i = 0; i < 12; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x30 + i, data->f2x9cx30[i]); for (i = 0; i < 12; i++) @@ -1093,7 +1093,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data *persiste } /* Stage 11 */ - if (IS_ENABLED(CONFIG_DIMM_DDR3)) { + if (CONFIG(DIMM_DDR3)) { for (node = 0; node < MAX_NODES_SUPPORTED; node++) { for (channel = 0; channel < 2; channel++) { struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; diff --git a/src/northbridge/amd/amdmct/wrappers/mcti.h b/src/northbridge/amd/amdmct/wrappers/mcti.h index db92fa789e..92dc0b853c 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti.h +++ b/src/northbridge/amd/amdmct/wrappers/mcti.h @@ -56,7 +56,7 @@ UPDATE AS NEEDED #endif #ifndef MAX_DIMMS_SUPPORTED -#if IS_ENABLED(CONFIG_DIMM_DDR3) +#if CONFIG(DIMM_DDR3) #define MAX_DIMMS_SUPPORTED 6 #else #define MAX_DIMMS_SUPPORTED 8 @@ -72,7 +72,7 @@ UPDATE AS NEEDED #endif #ifndef MEM_MAX_LOAD_FREQ -#if IS_ENABLED(CONFIG_DIMM_DDR3) +#if CONFIG(DIMM_DDR3) #define MEM_MAX_LOAD_FREQ 933 #define MEM_MIN_PLATFORM_FREQ_FAM10 400 #define MEM_MIN_PLATFORM_FREQ_FAM15 333 @@ -112,13 +112,13 @@ UPDATE AS NEEDED static const uint16_t ddr2_limits[4] = {400, 333, 266, 200}; static const uint16_t ddr3_limits[16] = {933, 800, 666, 533, 400, 333, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; -#if IS_ENABLED(CONFIG_DIMM_DDR3) +#if CONFIG(DIMM_DDR3) #include #else #include #endif -#if IS_ENABLED(CONFIG_DIMM_DDR2) +#if CONFIG(DIMM_DDR2) void mctSaveDQSSigTmg_D(void); void mctGetDQSSigTmg_D(void); u8 mctSetNodeBoundary_D(void); @@ -144,7 +144,7 @@ void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc void mctHookAfterAnyTraining(void); uint64_t mctGetLogicalCPUID_D(u8 node); -#if IS_ENABLED(CONFIG_DIMM_DDR3) +#if CONFIG(DIMM_DDR3) void vErratum372(struct DCTStatStruc *pDCTstat); void vErratum414(struct DCTStatStruc *pDCTstat); u32 mct_AdjustSPDTimings(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, u32 val); diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index b7d24764ed..e42085dce5 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -102,9 +102,9 @@ u16 mctGet_NVbits(u8 index) if (get_option(&nvram, "max_mem_clock") == CB_SUCCESS) { int limit = val; - if (IS_ENABLED(CONFIG_DIMM_DDR3)) + if (CONFIG(DIMM_DDR3)) limit = ddr3_limits[nvram & 0xf]; - else if (IS_ENABLED(CONFIG_DIMM_DDR2)) + else if (CONFIG(DIMM_DDR2)) limit = ddr2_limits[nvram & 0x3]; val = min(limit, val); } @@ -130,16 +130,16 @@ u16 mctGet_NVbits(u8 index) //val = 2; /* S4 (Unbuffered SO-DIMMS) */ break; case NV_BYPMAX: -#if !IS_ENABLED(CONFIG_GFXUMA) +#if !CONFIG(GFXUMA) val = 4; -#elif IS_ENABLED(CONFIG_GFXUMA) +#elif CONFIG(GFXUMA) val = 7; #endif break; case NV_RDWRQBYP: -#if !IS_ENABLED(CONFIG_GFXUMA) +#if !CONFIG(GFXUMA) val = 2; -#elif IS_ENABLED(CONFIG_GFXUMA) +#elif CONFIG(GFXUMA) val = 3; #endif break; @@ -193,9 +193,9 @@ u16 mctGet_NVbits(u8 index) val = !!nvram; break; case NV_BurstLen32: -#if !IS_ENABLED(CONFIG_GFXUMA) +#if !CONFIG(GFXUMA) val = 0; /* 64 byte mode */ -#elif IS_ENABLED(CONFIG_GFXUMA) +#elif CONFIG(GFXUMA) val = 1; /* 32 byte mode */ #endif break; @@ -214,9 +214,9 @@ u16 mctGet_NVbits(u8 index) case NV_BottomIO: case NV_BottomUMA: /* address bits [31:24] */ -#if !IS_ENABLED(CONFIG_GFXUMA) +#if !CONFIG(GFXUMA) val = (CONFIG_MMCONF_BASE_ADDRESS >> 24); -#elif IS_ENABLED(CONFIG_GFXUMA) +#elif CONFIG(GFXUMA) #if (CONFIG_MMCONF_BASE_ADDRESS < (MAXIMUM_GFXUMA_SIZE + MINIMUM_DRAM_BELOW_4G)) #error "MMCONF_BASE_ADDRESS is too small" #endif @@ -360,12 +360,12 @@ void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) if (pDCTstat->DimmRegistered[i + 1]) ch2_registered = 1; } - if (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)) { + if (CONFIG(DEBUG_RAM_SETUP)) { printk(BIOS_DEBUG, "mctGet_MaxLoadFreq: Channel 1: %d DIMM(s) detected\n", ch1_count); printk(BIOS_DEBUG, "mctGet_MaxLoadFreq: Channel 2: %d DIMM(s) detected\n", ch2_count); } -#if IS_ENABLED(CONFIG_DIMM_DDR3) +#if CONFIG(DIMM_DDR3) for (i = 0; i < MAX_DIMMS_SUPPORTED; i = i + 2) { if (pDCTstat->DIMMValid & (1 << i)) ch1_voltage |= pDCTstat->DimmConfiguredVoltage[i]; @@ -421,7 +421,7 @@ void mctHookAfterCPU(void) } -#if IS_ENABLED(CONFIG_DIMM_DDR2) +#if CONFIG(DIMM_DDR2) void mctSaveDQSSigTmg_D(void) { } @@ -470,7 +470,7 @@ void mctHookAfterDramInit(void) { } -#if IS_ENABLED(CONFIG_DIMM_DDR3) +#if CONFIG(DIMM_DDR3) void vErratum372(struct DCTStatStruc *pDCTstat) { msr_t msr = rdmsr(NB_CFG_MSR); @@ -504,7 +504,7 @@ void vErratum414(struct DCTStatStruc *pDCTstat) void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) { -#if IS_ENABLED(CONFIG_DIMM_DDR3) +#if CONFIG(DIMM_DDR3) /* FIXME : as of 25.6.2010 errata 350 and 372 should apply to ((RB|BL|DA)-C[23])|(HY-D[01])|(PH-E0) but I don't find constants for all of them */ if (pDCTstatA->LogicalCPUID & (AMD_DRBH_Cx | AMD_DR_Dx)) { vErratum372(pDCTstatA); @@ -513,7 +513,7 @@ void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc #endif } -#if IS_ENABLED(CONFIG_DIMM_DDR3) +#if CONFIG(DIMM_DDR3) u32 mct_AdjustSPDTimings(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, u32 val) { if (pDCTstatA->LogicalCPUID & AMD_DR_Bx) { @@ -534,7 +534,7 @@ uint64_t mctGetLogicalCPUID_D(u8 node) return mctGetLogicalCPUID(node); } -#if IS_ENABLED(CONFIG_DIMM_DDR2) +#if CONFIG(DIMM_DDR2) u8 mctSetNodeBoundary_D(void) { return 0; -- cgit v1.2.3