From 3d682fe8887b2ddd6c3c7e30c13b4e2f1c59779d Mon Sep 17 00:00:00 2001 From: Zheng Bao Date: Fri, 8 Oct 2010 03:35:12 +0000 Subject: Trivial. Fix the typo. Signed-off-by: Zheng Bao Acked-by: Zheng Bao git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5922 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/northbridge/amd/amdmct/mct/mctsrc.c | 4 ++-- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'src/northbridge/amd/amdmct') diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c index e761a05eb5..258be0468d 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc.c @@ -848,7 +848,7 @@ static void mct_InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { /* Initialize the DQS Positions in preparation for - * Reciever Enable Training. + * Receiver Enable Training. * Write Position is 1/2 Memclock Delay * Read Position is 1/2 Memclock Delay */ @@ -863,7 +863,7 @@ static void InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 Channel) { /* Initialize the DQS Positions in preparation for - * Reciever Enable Training. + * Receiver Enable Training. * Write Position is no Delay * Read Position is 1/2 Memclock Delay */ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index 585fc31582..b11da61156 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -800,7 +800,7 @@ static void mct_InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { /* Initialize the DQS Positions in preparation for - * Reciever Enable Training. + * Receiver Enable Training. * Write Position is 1/2 Memclock Delay * Read Position is 1/2 Memclock Delay */ @@ -814,7 +814,7 @@ static void InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 Channel) { /* Initialize the DQS Positions in preparation for - * Reciever Enable Training. + * Receiver Enable Training. * Write Position is no Delay * Read Position is 1/2 Memclock Delay */ -- cgit v1.2.3