From f3cce2f3c4ff4af4a386bddd49c92a55ad9cefa2 Mon Sep 17 00:00:00 2001 From: Scott Duplichan Date: Sat, 13 Nov 2010 19:07:59 +0000 Subject: MTRR related improvements for AMD family 10h and family 0Fh systems -- When building for UMA, reduce the limit for DRAM below 4GB from E0000000 to C0000000. This is needed to accomodate the UMA frame buffer. -- Correct problem where msr C0010010 bits 21 and 22 (MtrrTom2En and Tom2ForceMemTypeWB) are not set consistently across cores. -- Enable TOM2 only if DRAM is present above 4GB. -- Use AMD Tom2ForceMemTypeWB feature to avoid the need for variable MTRR ranges above 4GB. -- Add above4gb flag argument to function x86_setup_var_mtrrs. Clearing this flag causes x86_setup_var_mtrrs() to omit MTRR ranges for DRAM above 4GB. AMD systems use this option to conserve MTRRs. -- Northbridge.c change to deduct UMA memory from DRAM size reported by ram_resource. This corrects a problem where mtrr.c generates an unexpected variable MTRR range. -- Correct problem causing build failure when CONFIG_GFXUMA=1 and CONFIG_VAR_MTRR_HOLE=0. -- Reserve the UMA DRAM range for AMD K8 as is already done for AMD family 10h. Tested with mahogany on ECS A780G-GM with 2GB and 4GB. Tested with mahogany_fam10 on ECS A780G-GM with 2GB and 4GB. Signed-off-by: Scott Duplichan Acked-by: Peter Stuge git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6067 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/northbridge/amd/amdmct/wrappers/mcti.h | 6 ------ src/northbridge/amd/amdmct/wrappers/mcti_d.c | 22 +++++++++++++--------- 2 files changed, 13 insertions(+), 15 deletions(-) (limited to 'src/northbridge/amd/amdmct/wrappers') diff --git a/src/northbridge/amd/amdmct/wrappers/mcti.h b/src/northbridge/amd/amdmct/wrappers/mcti.h index e9247182de..357f2cb9bc 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti.h +++ b/src/northbridge/amd/amdmct/wrappers/mcti.h @@ -42,12 +42,6 @@ COMMENT OUT ALL BUT 1 //#define SYSTEM_TYPE MOBILE #endif -/*---------------------------------------------------------------------------- -COMMENT OUT ALL BUT 1 -----------------------------------------------------------------------------*/ -#define UMA_SUPPORT 0 /*Not supported */ -//#define UMA_SUPPORT 1 /*Supported */ - /*---------------------------------------------------------------------------- UPDATE AS NEEDED ----------------------------------------------------------------------------*/ diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index 4a8757639a..0ef60acecd 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -64,16 +64,16 @@ static u16 mctGet_NVbits(u8 index) //val = 2; /* S4 (Unbuffered SO-DIMMS) */ break; case NV_BYPMAX: -#if (UMA_SUPPORT == 0) +#if (CONFIG_GFXUMA == 0) val = 4; -#elif (UMA_SUPPORT == 1) +#elif (CONFIG_GFXUMA == 1) val = 7; #endif break; case NV_RDWRQBYP: -#if (UMA_SUPPORT == 0) +#if (CONFIG_GFXUMA == 0) val = 2; -#elif (UMA_SUPPORT == 1) +#elif (CONFIG_GFXUMA == 1) val = 3; #endif break; @@ -113,9 +113,9 @@ static u16 mctGet_NVbits(u8 index) //val = 1; /* Enable */ break; case NV_BurstLen32: -#if (UMA_SUPPORT == 0) +#if (CONFIG_GFXUMA == 0) val = 0; /* 64 byte mode */ -#elif (UMA_SUPPORT == 1) +#elif (CONFIG_GFXUMA == 1) val = 1; /* 32 byte mode */ #endif break; @@ -132,13 +132,17 @@ static u16 mctGet_NVbits(u8 index) //val = 1; /* enable */ break; case NV_BottomIO: +#if (CONFIG_GFXUMA == 0) val = 0xE0; /* address bits [31:24] */ +#elif (CONFIG_GFXUMA == 1) + val = 0xC0; /* address bits [31:24] */ +#endif break; case NV_BottomUMA: -#if (UMA_SUPPORT == 0) +#if (CONFIG_GFXUMA == 0) val = 0xE0; /* address bits [31:24] */ -#elif (UMA_SUPPORT == 1) - val = 0xB0; /* address bits [31:24] */ +#elif (CONFIG_GFXUMA == 1) + val = 0xC0; /* address bits [31:24] */ #endif break; case NV_ECC: -- cgit v1.2.3