From 99e1a672ecf99f8fa083e601a3c695eb02e93a33 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sat, 5 Sep 2015 18:00:27 -0500 Subject: northbridge/amd/amdfam10: Limit maximum RAM clock to BKDG recommendations Change-Id: I45eb03a4b351e458e8448245896743bd6fa57637 Signed-off-by: Timothy Pearson Reviewed-on: http://review.coreboot.org/11943 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand Reviewed-by: Aaron Durbin --- src/northbridge/amd/amdmct/wrappers/mcti_d.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'src/northbridge/amd/amdmct/wrappers') diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index f9a9921e6e..444adc513a 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -301,6 +301,8 @@ static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) /* Determine the number of installed DIMMs */ int ch1_count = 0; int ch2_count = 0; + uint8_t ch1_registered = 0; + uint8_t ch2_registered = 0; int i; for (i = 0; i < 15; i = i + 2) { if (pDCTstat->DIMMValid & (1 << i)) @@ -308,13 +310,19 @@ static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) if (pDCTstat->DIMMValid & (1 << (i + 1))) ch2_count++; } + for (i = 0; i < MAX_DIMMS_SUPPORTED; i = i + 2) { + if (pDCTstat->DimmRegistered[i]) + ch1_registered = 1; + if (pDCTstat->DimmRegistered[i + 1]) + ch2_registered = 1; + } if (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)) { printk(BIOS_DEBUG, "mctGet_MaxLoadFreq: Channel 1: %d DIMM(s) detected\n", ch1_count); printk(BIOS_DEBUG, "mctGet_MaxLoadFreq: Channel 2: %d DIMM(s) detected\n", ch2_count); } /* Set limits if needed */ - pDCTstat->PresetmaxFreq = mct_MaxLoadFreq(max(ch1_count, ch2_count), pDCTstat->PresetmaxFreq); + pDCTstat->PresetmaxFreq = mct_MaxLoadFreq(max(ch1_count, ch2_count), (ch1_registered || ch2_registered), pDCTstat->PresetmaxFreq); } #ifdef UNUSED_CODE -- cgit v1.2.3