From 471f103e530b97c1125acdab259043dd7f252fe9 Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Fri, 3 Jun 2011 19:59:52 +0000 Subject: This patch sets max freq defaults for ddr2 and ddr3for fam10. Signed-off-by: Marc Jones Acked-by: Scott Duplichan git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6619 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/northbridge/amd/amdmct/wrappers/mcti.h | 12 ++++++++++++ src/northbridge/amd/amdmct/wrappers/mcti_d.c | 4 ++-- 2 files changed, 14 insertions(+), 2 deletions(-) (limited to 'src/northbridge/amd/amdmct/wrappers') diff --git a/src/northbridge/amd/amdmct/wrappers/mcti.h b/src/northbridge/amd/amdmct/wrappers/mcti.h index 357f2cb9bc..9c948fe2a1 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti.h +++ b/src/northbridge/amd/amdmct/wrappers/mcti.h @@ -57,6 +57,18 @@ UPDATE AS NEEDED #define MAX_CS_SUPPORTED 8 #endif +#ifndef MCT_DIMM_SPARE_NO_WARM +#define MCT_DIMM_SPARE_NO_WARM 0 +#endif + +#ifndef MEM_MAX_LOAD_FREQ +#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */ + #define MEM_MAX_LOAD_FREQ 800 +#else + #define MEM_MAX_LOAD_FREQ 400 +#endif +#endif + #define MCT_TRNG_KEEPOUT_START 0x00000C00 #define MCT_TRNG_KEEPOUT_END 0x00000CFF diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index 569d61c7b0..4af75fd0e2 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -48,7 +48,7 @@ static u16 mctGet_NVbits(u8 index) //val = 200; /* 200MHz(DDR400) */ //val = 266; /* 266MHz(DDR533) */ //val = 333; /* 333MHz(DDR667) */ - val = 400; /* 400MHz(DDR800) */ + val = MEM_MAX_LOAD_FREQ;; /* 400MHz(DDR800) */ break; case NV_ECC_CAP: #if SYSTEM_TYPE == SERVER @@ -237,7 +237,7 @@ static void mctHookAfterDIMMpre(void) static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) { - pDCTstat->PresetmaxFreq = 400; + pDCTstat->PresetmaxFreq = MEM_MAX_LOAD_FREQ; } #ifdef UNUSED_CODE -- cgit v1.2.3