From 400ce55566caa541304b2483e61bcc2df941998c Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Fri, 12 Oct 2018 10:54:30 +0200 Subject: cpu/amd: Use common AMD's MSR Phase 1. Due to the size of the effort, this CL is broken into several phases. Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/29065 Tested-by: build bot (Jenkins) Reviewed-by: Richard Spiegel --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 17 +++++++++-------- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 11 ++++++----- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 20 +++++++++++--------- src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c | 5 +++-- 4 files changed, 29 insertions(+), 24 deletions(-) (limited to 'src/northbridge/amd/amdmct/mct_ddr3') diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 7421c18a69..b94c68c931 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -32,18 +32,19 @@ * supported. */ -#include "mct_d_gcc.h" -#include "mct_d.h" #include #include #include #include #include #include +#include #include #include #include #include "s3utils.h" +#include "mct_d_gcc.h" +#include "mct_d.h" static u8 ReconfigureDIMMspare_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); @@ -7770,7 +7771,7 @@ void mct_SetClToNB_D(struct MCTStatStruc *pMCTstat, /* FIXME: Maybe check the CPUID? - not for now. */ /* pDCTstat->LogicalCPUID; */ - msr = BU_CFG2; + msr = BU_CFG2_MSR; _RDMSR(msr, &lo, &hi); lo |= 1 << ClLinesToNbDis; _WRMSR(msr, lo, hi); @@ -7786,7 +7787,7 @@ void mct_ClrClToNB_D(struct MCTStatStruc *pMCTstat, /* FIXME: Maybe check the CPUID? - not for now. */ /* pDCTstat->LogicalCPUID; */ - msr = BU_CFG2; + msr = BU_CFG2_MSR; _RDMSR(msr, &lo, &hi); if (!pDCTstat->ClToNB_flag) lo &= ~(1<LogicalCPUID; */ - msr = BU_CFG; + msr = BU_CFG_MSR; _RDMSR(msr, &lo, &hi); hi |= (1 << WbEnhWsbDis_D); _WRMSR(msr, lo, hi); @@ -7818,7 +7819,7 @@ void mct_ClrWbEnhWsbDis_D(struct MCTStatStruc *pMCTstat, /* FIXME: Maybe check the CPUID? - not for now. */ /* pDCTstat->LogicalCPUID; */ - msr = BU_CFG; + msr = BU_CFG_MSR; _RDMSR(msr, &lo, &hi); hi &= ~(1 << WbEnhWsbDis_D); _WRMSR(msr, lo, hi); @@ -8048,7 +8049,7 @@ static void mct_ResetDLL_D(struct MCTStatStruc *pMCTstat, return; } - addr = HWCR; + addr = HWCR_MSR; _RDMSR(addr, &lo, &hi); if (lo & (1<<17)) { /* save the old value */ wrap32dis = 1; @@ -8079,7 +8080,7 @@ static void mct_ResetDLL_D(struct MCTStatStruc *pMCTstat, } if (!wrap32dis) { - addr = HWCR; + addr = HWCR_MSR; _RDMSR(addr, &lo, &hi); lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(addr, lo, hi); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 04299937d8..ce93472b9d 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -17,9 +17,10 @@ #include #include #include +#include +#include #include "mct_d.h" #include "mct_d_gcc.h" -#include static void CalcEccDQSPos_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u16 like, @@ -431,7 +432,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, cr4 |= (1<<9); /* OSFXSR enable SSE2 */ write_cr4(cr4); - addr = HWCR; + addr = HWCR_MSR; _RDMSR(addr, &lo, &hi); if (lo & (1<<17)) { _Wrap32Dis = 1; @@ -830,7 +831,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, mct_EnableDimmEccEn_D(pMCTstat, pDCTstat, _DisableDramECC); } if (!_Wrap32Dis) { - addr = HWCR; + addr = HWCR_MSR; _RDMSR(addr, &lo, &hi); lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(addr, lo, hi); @@ -1648,7 +1649,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, cr4 |= (1<<9); /* OSFXSR enable SSE2 */ write_cr4(cr4); - addr = HWCR; + addr = HWCR_MSR; _RDMSR(addr, &lo, &hi); if (lo & (1<<17)) { _Wrap32Dis = 1; @@ -1861,7 +1862,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, mct_EnableDimmEccEn_D(pMCTstat, pDCTstat, _DisableDramECC); } if (!_Wrap32Dis) { - addr = HWCR; + addr = HWCR_MSR; _RDMSR(addr, &lo, &hi); lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(addr, lo, hi); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index bae2e8998a..1db1b54307 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -22,9 +22,10 @@ #include #include #include +#include +#include #include "mct_d.h" #include "mct_d_gcc.h" -#include static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 Pass); @@ -661,14 +662,15 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, cr4 |= (1 << 9); /* OSFXSR enable SSE2 */ write_cr4(cr4); - msr = rdmsr(HWCR); + msr = rdmsr(HWCR_MSR); /* FIXME: Why use SSEDIS */ if (msr.lo & (1 << 17)) { /* save the old value */ _Wrap32Dis = 1; } msr.lo |= (1 << 17); /* HWCR.wrap32dis */ msr.lo &= ~(1 << 15); /* SSEDIS */ - wrmsr(HWCR, msr); /* Setting wrap32dis allows 64-bit memory references in real mode */ + wrmsr(HWCR_MSR, msr); /* Setting wrap32dis allows 64-bit memory + references in real mode */ _DisableDramECC = mct_DisableDimmEccEn_D(pMCTstat, pDCTstat); @@ -996,9 +998,9 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, } if (!_Wrap32Dis) { - msr = rdmsr(HWCR); + msr = rdmsr(HWCR_MSR); msr.lo &= ~(1<<17); /* restore HWCR.wrap32dis */ - wrmsr(HWCR, msr); + wrmsr(HWCR_MSR, msr); } if (!_SSE2) { cr4 = read_cr4(); @@ -1254,7 +1256,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, cr4 |= (1 << 9); /* OSFXSR enable SSE2 */ write_cr4(cr4); - msr = HWCR; + msr = HWCR_MSR; _RDMSR(msr, &lo, &hi); /* FIXME: Why use SSEDIS */ if (lo & (1 << 17)) { /* save the old value */ @@ -1498,7 +1500,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, } if (!_Wrap32Dis) { - msr = HWCR; + msr = HWCR_MSR; _RDMSR(msr, &lo, &hi); lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(msr, lo, hi); @@ -1613,7 +1615,7 @@ void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, cr4 |= (1 << 9); /* OSFXSR enable SSE2 */ write_cr4(cr4); - msr = HWCR; + msr = HWCR_MSR; _RDMSR(msr, &lo, &hi); /* FIXME: Why use SSEDIS */ if (lo & (1 << 17)) { /* save the old value */ @@ -1718,7 +1720,7 @@ void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, } if (!_Wrap32Dis) { - msr = HWCR; + msr = HWCR_MSR; _RDMSR(msr, &lo, &hi); lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(msr, lo, hi); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c index 039a747736..6c3db47542 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c @@ -21,6 +21,7 @@ #include #include #include +#include #include "mct_d.h" #include "mct_d_gcc.h" @@ -131,7 +132,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, cr4 |= (1<<9); /* OSFXSR enable SSE2 */ write_cr4(cr4); - addr = HWCR; + addr = HWCR_MSR; _RDMSR(addr, &lo, &hi); if (lo & (1<<17)) { /* save the old value */ _Wrap32Dis = 1; @@ -181,7 +182,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, } if (!_Wrap32Dis) { - addr = HWCR; + addr = HWCR_MSR; _RDMSR(addr, &lo, &hi); lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(addr, lo, hi); -- cgit v1.2.3