From 5a7e72f1aef02b326a67d883d92fe8c0aad9f3a9 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 23 Aug 2016 21:36:02 +0200 Subject: northbridge/amd: Add required space before opening parenthesis '(' Change-Id: Ic85f725bbdf72fbac5a4d9482c61343c5eb35e25 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/16305 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c | 50 +++++++++++++-------------- 1 file changed, 25 insertions(+), 25 deletions(-) (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c') diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c index 8cda2f8db0..15eb67e15b 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c @@ -77,7 +77,7 @@ static u32 SetupMaxRdPattern(struct MCTStatStruc *pMCTstat, buf = (u32 *)(((u32)buffer + 0x10) & (0xfffffff0)); - for(i = 0; i < (16 * 3); i++) { + for (i = 0; i < (16 * 3); i++) { buf[i] = TestMaxRdLAtPattern_D[i]; } @@ -89,14 +89,14 @@ void TrainMaxReadLatency_D(struct MCTStatStruc *pMCTstat, { u8 Node; - for(Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { struct DCTStatStruc *pDCTstat; pDCTstat = pDCTstatA + Node; - if(!pDCTstat->NodePresent) + if (!pDCTstat->NodePresent) break; - if(pDCTstat->DCTSysLimit) + if (pDCTstat->DCTSysLimit) maxRdLatencyTrain_D(pMCTstat, pDCTstat); } } @@ -119,7 +119,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, u32 pattern_buf; cr4 = read_cr4(); - if(cr4 & (1<<9)) { /* save the old value */ + if (cr4 & (1<<9)) { /* save the old value */ _SSE2 = 1; } cr4 |= (1<<9); /* OSFXSR enable SSE2 */ @@ -127,7 +127,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, addr = HWCR; _RDMSR(addr, &lo, &hi); - if(lo & (1<<17)) { /* save the old value */ + if (lo & (1<<17)) { /* save the old value */ _Wrap32Dis = 1; } lo |= (1<<17); /* HWCR.wrap32dis */ @@ -144,11 +144,11 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, print_debug_dqs("\tMaxRdLatencyTrain51: Channel ",Channel, 1); pDCTstat->Channel = Channel; - if( (pDCTstat->Status & (1 << SB_128bitmode)) && Channel) + if ( (pDCTstat->Status & (1 << SB_128bitmode)) && Channel) break; /*if ganged mode, skip DCT 1 */ TestAddr0 = GetMaxRdLatTestAddr_D(pMCTstat, pDCTstat, Channel, &RcvrEnDly, &valid); - if(!valid) /* Address not supported on current CS */ + if (!valid) /* Address not supported on current CS */ continue; /* rank 1 of DIMM, testpattern 0 */ WriteMaxRdLat1CLTestPattern_D(pattern_buf, TestAddr0); @@ -156,10 +156,10 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, MaxRdLatDly = mct_GetStartMaxRdLat_D(pMCTstat, pDCTstat, Channel, RcvrEnDly, &Margin); print_debug_dqs("\tMaxRdLatencyTrain52: MaxRdLatDly start ", MaxRdLatDly, 2); print_debug_dqs("\tMaxRdLatencyTrain52: MaxRdLatDly Margin ", Margin, 2); - while(MaxRdLatDly < MAX_RD_LAT) { /* sweep Delay value here */ + while (MaxRdLatDly < MAX_RD_LAT) { /* sweep Delay value here */ mct_setMaxRdLatTrnVal_D(pDCTstat, Channel, MaxRdLatDly); ReadMaxRdLat1CLTestPattern_D(TestAddr0); - if( CompareMaxRdLatTestPattern_D(pattern_buf, TestAddr0) == DQS_PASS) + if ( CompareMaxRdLatTestPattern_D(pattern_buf, TestAddr0) == DQS_PASS) break; SetTargetWTIO_D(TestAddr0); FlushMaxRdLatTestPattern_D(TestAddr0); @@ -170,17 +170,17 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, mct_setMaxRdLatTrnVal_D(pDCTstat, Channel, MaxRdLatDly + Margin); } - if(_DisableDramECC) { + if (_DisableDramECC) { mct_EnableDimmEccEn_D(pMCTstat, pDCTstat, _DisableDramECC); } - if(!_Wrap32Dis) { + if (!_Wrap32Dis) { addr = HWCR; _RDMSR(addr, &lo, &hi); lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(addr, lo, hi); } - if(!_SSE2){ + if (!_SSE2){ cr4 = read_cr4(); cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ write_cr4(cr4); @@ -190,7 +190,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, { u8 ChannelDTD; printk(BIOS_DEBUG, "maxRdLatencyTrain: CH_MaxRdLat:\n"); - for(ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) { + for (ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) { printk(BIOS_DEBUG, "Channel: %02x: %02x\n", ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]); } } @@ -245,7 +245,7 @@ static u8 CompareMaxRdLatTestPattern_D(u32 pattern_buf, u32 addr) print_debug_dqs_pair("\t\t\t\t\t\ttest_buf = ", (u32)test_buf, " value = ", val_test, 5); print_debug_dqs_pair("\t\t\t\t\t\ttaddr_lo = ", addr_lo, " value = ", val, 5); - if(val != val_test) { + if (val != val_test) { ret = DQS_FAIL; break; } @@ -273,7 +273,7 @@ static u32 GetMaxRdLatTestAddr_D(struct MCTStatStruc *pMCTstat, bn = 8; - if(pDCTstat->Status & (1 << SB_128bitmode)) { + if (pDCTstat->Status & (1 << SB_128bitmode)) { ch_start = 0; ch_end = 2; } else { @@ -283,12 +283,12 @@ static u32 GetMaxRdLatTestAddr_D(struct MCTStatStruc *pMCTstat, *valid = 0; - for(ch = ch_start; ch < ch_end; ch++) { - for(d=0; d<4; d++) { - for(Byte = 0; ByteCH_D_B_RCVRDLY[ch][d][Byte]; - if(tmp>Max) { + if (tmp>Max) { Max = tmp; Channel_Max = Channel; d_Max = d; @@ -297,11 +297,11 @@ static u32 GetMaxRdLatTestAddr_D(struct MCTStatStruc *pMCTstat, } } - if(mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel_Max, d_Max << 1)) { + if (mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel_Max, d_Max << 1)) { TestAddr0 = mct_GetMCTSysAddr_D(pMCTstat, pDCTstat, Channel_Max, d_Max << 1, valid); } - if(*valid) + if (*valid) *MaxRcvrEnDly = Max; return TestAddr0; @@ -318,7 +318,7 @@ u8 mct_GetStartMaxRdLat_D(struct MCTStatStruc *pMCTstat, u32 index_reg; u32 dev; - if(pDCTstat->GangedMode) + if (pDCTstat->GangedMode) Channel = 0; index_reg = 0x98; @@ -331,14 +331,14 @@ u8 mct_GetStartMaxRdLat_D(struct MCTStatStruc *pMCTstat, /* If registered DIMMs are being used then add 1 MEMCLK to the sub-total*/ val = Get_NB32_DCT(dev, Channel, 0x90); - if(!(val & (1 << UnBuffDimm))) + if (!(val & (1 << UnBuffDimm))) SubTotal += 2; /*If the address prelaunch is setup for 1/2 MEMCLKs then add 1, * else add 2 to the sub-total. if (AddrCmdSetup || CsOdtSetup * || CkeSetup) then K := K + 2; */ val = Get_NB32_index_wait_DCT(dev, Channel, index_reg, 0x04); - if(!(val & 0x00202020)) + if (!(val & 0x00202020)) SubTotal += 1; else SubTotal += 2; -- cgit v1.2.3