From eb75f652d392d2f4f257194e112f3f0db7479145 Mon Sep 17 00:00:00 2001 From: Zheng Bao Date: Fri, 23 Apr 2010 17:32:48 +0000 Subject: DDR3 support for AMD Fam10. Signed-off-by: Zheng Bao Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5481 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c | 85 ++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c') diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c new file mode 100644 index 0000000000..008705c613 --- /dev/null +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c @@ -0,0 +1,85 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +u8 mct_checkNumberOfDqsRcvEn_1Pass(u8 pass) +{ + u8 ret = 1; + if (pass == SecondPass) + ret = 0; + + return ret; +} + +u32 SetupDqsPattern_1PassA(u8 pass) +{ + return (u32) TestPattern1_D; +} + +u32 SetupDqsPattern_1PassB(u8 pass) +{ + return (u32) TestPattern0_D; +} + +u8 mct_Get_Start_RcvrEnDly_1Pass(u8 pass) +{ + return 0; +} + +static u8 mct_Average_RcvrEnDly_1Pass(struct DCTStatStruc *pDCTstat, u8 Channel, u8 Receiver, + u8 Pass) +{ + u8 i, MaxValue; + u8 *p; + u8 val; + + MaxValue = 0; + p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1]; + + for(i=0; i < 8; i++) { + /* get left value from DCTStatStruc.CHA_D0_B0_RCVRDLY*/ + val = p[i]; + /* get right value from DCTStatStruc.CHA_D0_B0_RCVRDLY_1*/ + val += Pass1MemClkDly; + /* write back the value to stack */ + if (val > MaxValue) + MaxValue = val; + + p[i] = val; + } + /* pDCTstat->DimmTrainFail &= ~(1<DqsRcvEn_Pass == 0xff) && (pass== FirstPass)) + ret = 2; + return ret; +} + +u8 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, + u8 RcvrEnDly, u8 RcvrEnDlyLimit, + u8 Channel, u8 Receiver, u8 Pass) + +{ + return mct_Average_RcvrEnDly_1Pass(pDCTstat, Channel, Receiver, Pass); +} -- cgit v1.2.3